Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18982 Discussions

QuartusII Prime Pro 16.1/17.1 EMIF(DDR4) Pin Constrain Problem

Honored Contributor II

Hi all, I'm trying to use Quartus II 16.1/17.1 Prime Pro with EMIF to control DDR4. The configuration is descirbed below: 

FPGA: 10AX066N1F40 

DDR4 Config: Single-Rank, x64, Scheme 2 

Number of EMIF: 2 individual controllers 

I/O Bank Arrangement by BluePrint: 

**Controller A:3C,3D and 3E 

Controller B:3F, 3G and 3H 


The condition I got is: 

At the first time I did compliation and I/O fitting in Quartus II(using BluePrint I/O assignment), it all passed. Since I'm a newbie of DDR4, I'm trying to follow the design guidline provided by Intel, "Arria 10 External Memory Interface Handbook Vol. 1~3" and the step-by-step material in website: 


By comparing the I/O placement constrain, I found that in default BluePrint assignment, the RZQ pin position is conflicted to the pin placement sugestion. 

**BluePrint Default of Controller A 

RZQ is assigned at pin AT12, which is the No. 26 pin of bank 3A 

**BluePrint Default of Controller B 

RZQ is assigned at pin L2, which is the No. 26 pin of bank 3F 


However, in the design guidline materials I read, the RZQ is suggested to be placed within the same I/O bank as Command/Address signal of EMIF, which in my case should be bank 3D and 3G of controller A and B, separately. 


So I tried to re-assign these two pins to AD6 and D6 (No. 26 pin of bank D and G) and go through the complilation/fitting, but there's no luck. A pin constrain erro message appears both in BluePrint and QuartusII. 


Is there any misunderstanding part I got? Otherwise the default RZQ pin is far away from control I/O groups, it might be troublesome in PCB routing. 


0 Kudos
2 Replies
Honored Contributor II

Hi Alex, 


Your understanding is correct. Ideally we want to place RZQ pin in address IOBANK which is middle of 3 IOBANK so that the signal routing can be spread balance throughout 3 IOBANK. 


I am not sure what's wrong with your design but you can try place RZQ_A in pin 26 of Bank 3C or 3E and RZQ_B in pin 26 of Bank 3F,3H. 






(This message was posted on behalf of Intel Corporation)
Honored Contributor II

Hi spdl2001, 


thanks for your reply, it's glad to know my understanding is correct!! 

However the project I created still having error message when I manually assign RZQ_A/B pins. 

But when I create a whole new project, looks like the Blueprint works normally and no similar error occurs. I'll see which step I did wrong in previous project and thanks again for your suggestions.