I am new user try to run my simple test on Altera Max V eval kit. I wrote a simple code want to verify a simple function:http://www.alteraforum.com/forum/attachment.php?attachmentid=12665&stc=1 in file counter.v
module counter( CLOCK_10KHZ, counter_out, RESET); input CLOCK_10KHZ; input RESET; output counter_out; reg counter_out; always @(posedge CLOCK_10KHZ) begin if (!RESET) begin //Reset button is not pushed counter_out <=# 1 ~(counter_out + 1); //increment counter, neg light up the LED, and pos turn off end else begin counter_out <=# 1 ~16'b0; end end endmoduleWhen I push the reset button, the LED goes off, that proved clock trigger signal is correct, however, after I release the PB1, all LEDs still on and didn't change status(It suppose to light up and turn off while counter increasing). Platform: Windows 7,64bit, Quartus Prime Lite Edition 16.0. MAX V Eval Board Could anyone take a look what might be wrong with my program? Thank you!
I might suggest that you've not simulated this. Doing so would have quickly pointed out your fault. Firstly, remove the "#1" from your code. This means nothing to your MAX V device or any logic synthesizer. Secondly, change the above statement to a simple
counter_out <=# 1 ~(counter_out + 1);This is not doing what you want it too and is just resulting in 'counter_out' holding a static value (both in and out of reset).
counter_out <= counter_out + 1;Then, outside of that always block, deal with the inversion that the LEDs on your hardware require.
assign led = ~counter_out;Finally, swap 'led' for 'counter_out' in your module's port list. Cheers, Alex