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CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Question - Transceiver Native PHY

schlee68
Beginner
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Hi-Everybody

I use 3 IPs
Transceiver Native PHY + Reset Controller + fPLL
This Design is Transmitter only, and parallel 40 bit

 

In Transceiver Native PHY, "tx_clkout" is used as a clock for tx_parallel_data

 

I shot "tx_clkout" with a scope.
in the fPLL 2GHz, x_clkout = 100MHz

 

So I thought.
If you receive 40 bits in parallel at 100Mhz,
Serial should be 4GHz.

 

Therefore, the clock frequency is increased to 4GHz. (fPLL)
Then it was x_clkout = 200 MHz.

 

How to set the clock frequency?

 

I tested the frequency below
4GHz tx_clkout:200MHz
2GHz tx_clkout:100MHz
1GHz tx_clkout:50MHz

 

 

 

 

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Kshitij_Intel
Employee
338 Views

Hi,


Can you please share below info.


1) Which Operating system you are using?

2) Which Quartus Software version you are using?

3) Which device(OPN) you are targeting?


Thank you

Kshitij Goel



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Kshitij_Intel
Employee
321 Views

Hi,


As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you

Kshitij Goel



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