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xytech
New Contributor I
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Question about Autonomous Mode Configuration

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Hi

We use A10 10AX057H3F34E2SG for both PCIe GEN3.0 connected with host PC. To circumvent PCIe 100ms wake up time requirement, we may use Autonomous Mode for A10 FPGA Configuration. Some questions here.

 

In UG-01145_avmm intel doc, chapter 12 mentioned CvP and Autonomous Mode (AM). Both of these two means takes similar thought that split traditional bits-stream files into two parts, firstly Peripheral Image (contains PCIe Hard IP) anf Core Fabric Image. Smaller Peripheral Image are firstly configured so that Host PC could start PCIe link training within 100ms.

(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf)

 

We found some dedicated user guide on CvP topics such as (ug-20010), but we plan to use AM as CvP is not applicable to our situation. However, I do not found any doc about AM except UG-01145_avmm(rather simple although). Where could I found detailed info about AM, such as bit-stream sizes of two parts in AM, timing info, hardware design constrains?

 

Further more, UG-01145_avmm section 12.2 indeed mentioned that “ALL PCIe IP cores on a device can operate in autonomous mode. However, only the bottom Hard IP for PCI Express on either side can satisfy the 100 ms PCIe wake up time requirement.” So what is the exact context of this “BOTTM”? Under TOP VIEW or Bottom VIEW? And you know, sometimes “BOTTOM side” could become “TOP side” if chips are spined/rotated……

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JohnT_Intel
Employee
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Hi, Please refer to chapter 4.2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf document. It will mention which PCIe hard IP will be able to meet the 100ms wake up time. Based on that location then you will need to either mapped it to the pin planner or pin-out file for the exact pin to be connected to the PCIe host.

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12 Replies
xytech
New Contributor I
40 Views

Copied from this link: https://forums.intel.com/s/question/0D50P00003yyPwwSAE/cvp-initialization-vs-update-modes-in-cyclone...

 

 

hi , recently I had a same hard time with yours. After struggled in intel's docs, I do found something useful to solve our problem. See this Autonoumous Mode. It is different from CVP and it exactly answered your question "What I need is to have the periphery (Hard IP) image and core image load from on-board flash (AS x4 mode), with the Hard IP PCIe controller meeting the PCIe wake up time". just search "Autonoumous" in following docs. Hope it helps.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01110_avmm-1...

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-cvp-15.1.pdf...

 

Another point, if you want to use CVP, you will need software driver programs on Host PC. Intel provide driver demos for Linux, but no support for x86 OS.

 

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JohnT_Intel
Employee
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Hi, You can get further information from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf. The bitstream will be the same as full bitstream size. Timing and hardware design constrains will follow PCIe specification. The full bitstream will contain both periphery and core design where it will configured the periphery bitstream 1st before continue with core bitstream. So once the periphery bitstream is completed then the PCIe link training can start.
xytech
New Contributor I
40 Views

Hi John, Thanks for reply.

 

I do searched through and compare ug_a10_pcie_avst.pdf and ug_a10_pcie_avmm.pdf (the one you mentioned), both docs are nearly the same. first doc on section 12.2, and second doc on section 14.2.

Thanks for point out that total bitstream size will not change. However, what I need to konw is the individual size of each part when use AM, that is, what's the size of periphery image? and what's the size of core image. Two

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

 

Furthermore, could you please take a look at my second question? Copied here.

Both docs mentioned “only the bottom Hard IP for PCI Express on either side can satisfy the 100 ms PCIe wake up time requirement.”  What is the exact context of this “BOTTM” means?  Under TOP VIEW or Bottom VIEW? on what position should the pin A1 be? As you know, sometimes “BOTTOM side” could become “TOP side” if chips are spined or flipped on PCB layout……

 

Thanks again.

JohnT_Intel
Employee
41 Views
Hi, Please refer to chapter 4.2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf document. It will mention which PCIe hard IP will be able to meet the 100ms wake up time. Based on that location then you will need to either mapped it to the pin planner or pin-out file for the exact pin to be connected to the PCIe host.

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xytech
New Contributor I
40 Views

Hi John, Thanks for answer. almost clear. Great!

 

I still have one question. On section4.2 , it mentioned a limitation that : "Intel Arria 10 devices do not support configurations that configure a bottom (left or right) hard IP block with a Gen3 x4 or Gen3 x8 IP core and also configure the top hard IP block on the same side with a Gen3 x1 or Gen3 x2 IP core variation." and then shows some channels examples for ONLY GT device with 72/96/48 XCVRs, figure16-18 .

 

Our GX device (10AX057H3F34E2SG ) contains two Hard PCIe IP, one bottom and one top. Does this limitation also applicable to our device?

I think it does, but need confirm from Intel.

 A10 XCVR.png

 

Thanks again!

JohnT_Intel
Employee
40 Views
Hi, Yes, it will be the same as GX device
xytech
New Contributor I
40 Views

Thanks, John. Very helpful!

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