Question about Slow Clock for Altlvds_RX

[Altera_Forum]

I use Altlvds_TX and RX as interface between two boards. Parallel data rate is 10M, deserializer is 10, data rate is 100M. The FPGA I used is Cyclone IV E which doesn't support Soft CDR and DPA mode. So a slow clock( 10M ) has to be transmitted from transmitter in one board to receiver in another board. The clock is transmitted in LVDS. But I have some problem when I try to use this clock in receiver side. I read Altera LVDS SERDES transmitter/receiver user guilde and also AN479 for design notes for implementing LVDS in Cyclone. But I could not find answer from them because it is either in general or not applicable to cyclone. Below is what I tried. 

 1. I tried to use internal PLL mode for TX and RX. Input clock for RX is the 10M slow clock transmitted from transmitter in anothe board. The input clock for TX is from a local PLL implemented for other logic such as NiosII. In this case, the PLL can not be shared between TX and RX because the PLL input is different. So in total it needs 3 PLL: one for TX, one for RX and one for other logic. But the device I used is EP4CE6 which has only 2 PLLs. So the design can't fit the device.   2. I tried to use external PLL. For RX, according to user guilde, a PLL is needed to generate fast clock( 50MHz ) for RX from slow clock (10M, transmitted from transmitter in another board ). But PLL inclk can not accept LVDS input. So I run into trouble again.   3. transmit fast clock 50M from transmitter and then divide it 10M. Connect the 50M clock to RX input clock directly. Use the 10M for sync of received parallel data. But it could not receive correct data.  What should I do?  In my case, is Altlvds_TX/RX still valuable? For cyclone devices, it is just serializer and deserilizer, no soft CDR and DPA is supported.  Thanks