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Question about register's initial value

RobertLiang
New Contributor I
315 Views

Hello, I have a question about the initial value of registers in verilog. I have heart two kinds of views.

code for example:
//verilog
reg [7:0] test_reg = 8'b1111_0000;

1. the initial value is determined by part and technology, hence no matter what value i set when definite this variable, it will be set all '0' or all '1' when power-up.

2. the value i set when definition is the value when power-up. ( i heart new fpga parts don't suggest use 'if(reset==0)' in always block.)

i can't find the precise answer of this question in search engine, please give me a official answer. 

Thank you!

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1 Solution
KhaiChein_Y_Intel
297 Views

Hi,


You can set the Power-Up Level option for one or more registers. If registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous clear cannot power up to High. Similarly, if registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous preset cannot power up to Low. Note that Quartus Prime Integrated Synthesis reads default values for registered signals defined in VHDL code and converts the default values into Power-Up Level settings. The software also synthesizes variables that are assigned values in Verilog HDL initial blocks into power-up conditions.


You may refer to Chapter 1.5.1: Register Power-Up Values for details

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommenda...


Thanks.

Best regards,

KhaiY


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3 Replies
KhaiChein_Y_Intel
300 Views

Hi,


You can set the Power-Up Level option for one or more registers. If registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous clear cannot power up to High. Similarly, if registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous preset cannot power up to Low. Note that Quartus Prime Integrated Synthesis reads default values for registered signals defined in VHDL code and converts the default values into Power-Up Level settings. The software also synthesizes variables that are assigned values in Verilog HDL initial blocks into power-up conditions.


Thanks.

Best regards,

KhaiY


KhaiChein_Y_Intel
298 Views

Hi,


You can set the Power-Up Level option for one or more registers. If registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous clear cannot power up to High. Similarly, if registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous preset cannot power up to Low. Note that Quartus Prime Integrated Synthesis reads default values for registered signals defined in VHDL code and converts the default values into Power-Up Level settings. The software also synthesizes variables that are assigned values in Verilog HDL initial blocks into power-up conditions.


You may refer to Chapter 1.5.1: Register Power-Up Values for details

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommenda...


Thanks.

Best regards,

KhaiY


KhaiChein_Y_Intel
282 Views

Hi,


Since your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


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