RAM initialization with .mif using logic elements?

[jozephka99]

I write a ram module with Intel's template. It is working fine amd not uses any logic elements without initializing it. But when I initialize it with a .mif file that I created, it uses logic elements which I don't want it because I lack of logic elements. Am I doing wrong with initialization or is this normal when we doing ram init. If it is, is there any way to store data without using logic elements?

library ieee;
use ieee.std_logic_1164.all;

entity dev_i2c_conf_ram is
	generic 
	(
		DATA_WIDTH : natural := 16;
		ADDR_WIDTH : natural := 298
	);

	port 
	(
		clk		: in std_logic;
		addr		: in natural range 0 to (ADDR_WIDTH - 1);
		data_in	: in std_logic_vector((DATA_WIDTH - 1) downto 0);
		we			: in std_logic;
		data_out	: out std_logic_vector((DATA_WIDTH - 1) downto 0)
	);
end entity;

architecture rtl of dev_i2c_conf_ram is

	-- Build a 2-D array type for the RAM
	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
	type ram_t is array(((ADDR_WIDTH) - 1) downto 0) of word_t;

	-- Declare the RAM signal.	
	signal ram : ram_t;
	
	-- Initialize RAM
	attribute ram_init_file : string;
	attribute ram_init_file of ram :
	signal is "dev_i2c_conf.mif";
	
	-- Register to hold the address/page 
	signal addr_reg : natural range 0 to ((ADDR_WIDTH) - 1);

begin

	process(clk)
	begin
	if(rising_edge(clk)) then

		if(we = '1') then
			ram(addr) <= data_in;
		end if;

		-- Register the address for reading
		addr_reg <= addr;
	end if;
	end process;

	data_out <= ram(addr_reg);

end rtl;

[sstrell]

I'm not sure why it would use memory blocks when you're not initializing it but use logic when you do initialize it, but I wouldn't use "natural" for a logic design like this.  Everything should be std_logic or std_logic_vector.

In the Quartus text editor, check out the templates for inferring a RAM with initialization.  Maybe you'll get a clue about what's happening from there.  Or you can add the RAM as an IP from the IP Catalog.

[jozephka99]

It is already based from Quartus template. They also use natural. Maybe I can change it to integer but I don't think it makes any difference. Quartus also have initialized RAM template but they are not initialize it from .mif file. So it is useless for me. But in a user guide of Altera the above "Attribute" way used, so I used it too. 

[RichardTanSY_Intel]

Hi @jozephka99 

Could you help to share your design .qar file so I can check on this? 

At the same time, could you help to share a screenshot showing the issue that it is using logic element instead of memory?

Have you try to use our On Chip Memory IP in the IP Catalog instead of inference and see whether the same issue occur? 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[RichardTanSY_Intel]

Hi @jozephka99 

Could you help to share your design .qar file so I can check on this? 

At the same time, could you help to share a screenshot showing the issue that it is using logic element instead of memory?

Have you try to use our On Chip Memory IP in the IP Catalog instead of inference and see whether the same issue occur? 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[RichardTanSY_Intel]

Hi @jozephka99 

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.