RAM to DSP

[shxb]

hi,

  we have data path : RAM output->normal_reg->DSP_input_reg , 

  there is only one "normal_reg" , but it drives 8 DSPs, timing violation path reported for "RAM output->normal_reg".

  without insert clock cycles , what can we do to fix it?

  maybe move the "DSP_input_reg"  outside DSP block helps? i do not know how to constrains it on RTL, or some other suggestions? 

  thanks

[sstrell]

Enable register duplication to break up the fanout of normal_reg.

[RichardTanSY_Intel]

Hi @shxb 

May I know the suggestion from sstrell helps? 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.