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RX clock out varying speed after Programming FPGA Multiple times

Rk_Athram
New Contributor I
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Hi,
I am using Arria 10 GX dev kit , with transceivers in my design.

I am working on 5G speed, data width is 40Bits.

so my rx_clkout should be fixed 125Mhz.

I am seeing a difference in rx_clkout,  it is varying from 125Mhz-160Mhz each time when i program FPGA the clock is NOT stable,
I have given rx_clkout to SMA pin on board and checked in Picoscope.

change in clock , Is it a expected behavior? 

If NO, what might be causing the issue?  

 

 

 

 

 

 

 

 

 

Regards,

Rajesh

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Kshitij_Intel
Employee
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Hi Rajesh,


This is not the expected Behavior, please check the rx_is_lockedtodata, rx_is_lockedtoref, signals.


Please go through the Intel® Arria® 10 Transceiver PHY User Guide

https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-phy-overview.html


It has all the info you need. Please check reset sequence also. Follow Chapter 4.


Thank you

Kshitij Goel


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Kshitij_Intel
Employee
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Hi Rajesh,


Any update on this.



Thank you

Kshitij Goel


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