Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20704 Discussions

Rbf jic issue

Altera_Forum
Honored Contributor II
1,606 Views

Hi, 

I am working with a cyclone IV device EP4CE55 in a project. 

I programmed jic and the fpga is configuring properly. 

I programmed rbf file of the same project,FPGA is not configuring.I can see some toggling on the Done signal. 

After programming rbf even if I power cycle the board,FPGA doesn't boots up. 

I am programming rbf after bit reversing as per altera recommendation. 

The programmed jic and rbf files were read back and verified.In 6 locations starting from address location 0x45 in page 0 data is different in jic and rbf. 

Please help to resolve tis issue. 

 

Will there be difference in rbf anf jic apart from bit reversal?
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
563 Views

Hi, 

 

1. Have to set msel to Passive serial mode? 

2. Check the pull-up resistor. 

 

Try to regenerate the .rbf file. 

 

Refer previous threads 

https://www.alteraforum.com/forum/showthread.php?t=44219 

https://alteraforum.com/forum/showthread.php?t=6499 

Steps: 

1. Open Convert Programming File tab. 

2. Choose Programming file type - JIC 

3. Choose all needed settings 

4. Check the Create config data RPD 

5. Press Generate. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
0 Kudos
Altera_Forum
Honored Contributor II
563 Views

Hi Anand, 

 

Thanks for your reply. 

MSEL is setting is as follows: 

MSEL3-0 MSEL2-0 MSEL1-1 and MSEL0-0 

Is there any difference between active serial and passive serial mode? 

We are using rbf file to update fpga and not rpd file. 

I tested by generating rbf and jic from same sof file. 

Jic is working fine.But with rbf fpga is not configuring. 

 

We have noticed one more finding. In the rbf if I change the data bytes at locations 0x45,46,47,48 and 49 as per jic. FPGA boots up with new image.
0 Kudos
Altera_Forum
Honored Contributor II
563 Views

Hi, 

 

 

--- Quote Start ---  

MSEL is setting is as follows: 

MSEL3-0 MSEL2-0 MSEL1-1 and MSEL0-0 

--- Quote End ---  

 

Refer Table 8-5 for MSEL setting. 

I think MSEL should be MSEL3-0 MSEL2-0 MSEL1-0 and MSEL0-0 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf 

 

 

--- Quote Start ---  

Is there any difference between active serial and passive serial mode? 

--- Quote End ---  

 

You can refer to the below links and device handbook for more information. 

https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/cfg-compare.html 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
0 Kudos
Reply