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Remote System Upgrade for MAX 10 FPGA

YSuzu21
New Contributor I
347 Views

「AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART

with the Nios II Processor」の「Figure 1. Reference Design Block Diagram」では、NiosⅡを使用してDual Configuration IP Core を制御しておりますが、、NiosⅡとDual Configuration IP CoreのCLK周波数はちがってもよろしいですか。

使用しているFPGAは、10M16SCE144C8Gです。

​NiosⅡのCLK = 50MHz Dual Configuration IP CoreのCLK = 40MHz

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YSuzu21
New Contributor I
233 Views
2 Replies
ShafiqY_Intel
Employee
233 Views

Hi YSuzu21,

 

We use the same clock for NIOS II and Dual Configuration IP.

we use similar PLL output to these NIOS II IP and Dual Configuration IP:

 

RSU max 10 refdeg.JPG

 

Cheers

 

 

YSuzu21
New Contributor I
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