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Hi ,
we are using Cyclone V e FPGA and wanted to use Intel FPGA ALTECC IP core as decoder with input encoded data as 72bits ( 64bit data + 8 Bit parity). we are implementing ALTECC IP at our receiver data stream within fpga , whereas source of data is from external SBC (non fpga) device.
So What encoding technique should we implement at source SBC device for use to correctly detect/decode ECC data at receiver in FPGA. will hamming code implementation at source device will work?
kindly suggest different ECC coding technique for external device compatible with Intel FPGA ALTECC decoder IP core for above data configuration 72bits ( 64bit data + 8 Bit parity).
thanks ,
Snehal B.
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Hi,
Based on ALTECC Intel FPGA IP description,
The ALTECC megafunction allows you to encoding or decoding input by using Hamming Coding Scheme. Check image:
Hamming code implementation at source device should be not a problem.
Document link: https://www.intel.com/content/www/us/en/docs/programmable/683490/20-3/altecc-encoder-features.html
Best Regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.
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Hi,
Do you have any further consideration or concern on this thread?
Thanks,
Best Regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.
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Hi,
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
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