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Altera_Forum
Honored Contributor I
2,607 Views

Reset for PLL

I am working on a project involving Arria V FPGA. 

I need to have a PLL for generating clocks for my internal FPGA logic. 

I am confused about the reset signal of PLL. I have no external H/W reset pin. To which pin must I connect this reset signal. 

I am deriving the reset signal for logics from PLL locked signal. 

 

I am thinking of connecting this pin to POR signal. How to access the power on reset pin? 

 

Are there any other suggestions for connecting PLL reset pin? 

 

Thanks
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12 Replies
Altera_Forum
Honored Contributor I
492 Views

I don't know Arria V, but with other Altera FPGA devices the PLL reset signal is optional. 

You expose and connect it only in special situation, i.e. when you need to reconfigurate the PLL or when you switch off a clock and have to resynchronize.
Altera_Forum
Honored Contributor I
492 Views

Thank you Cris. 

I am using Quartus 12.0 ver and here I have no option of disabling the reset pin. 

Is it suggested that I always connect this pin to logic low?
Altera_Forum
Honored Contributor I
492 Views

Having just checked (I assumed the same as Cris) it seems the reset input port is 'required' for the Altera PLL suitable for Arria V - see the user guide (https://www.altera.com/en_us/pdfs/literature/ug/altera_pll.pdf). A quick play with Quartus confirms this. 

 

POR pin? There isn't one - only an internal POR circuit for the device. I don't think there's any access to it. So, if tying reset to '0' isn't sufficient and you must generate a reset, I suggest you consider a counter that generates a reset at power up. And, if the PLL ever looses lock you can consider resetting the counter to regenerate the reset. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
492 Views

Hi Nagakiran, 

 

The reset to PLL is important especially after the PLL lose lock, or there is any change to the refclk, or dynamic reconfiguration performed. You can create some user logic to control the reset when these three events occur.
Altera_Forum
Honored Contributor I
492 Views

In a similar situation, I have no HW reset pin so I was planning to use loss of lock to drive a reset to the PLL, and also reset the all the registers in my design to a known state. Does it make sense to do that?  

I'm wondering if it's even necessary to do this, but I've never coded an FPGA without a reset.
Altera_Forum
Honored Contributor I
492 Views

Driving the PLL reset with it's own locked output signal (inverted) sounds reasonable to me. I've just tried this - Quartus allows this with Cyclone V. So, it caters for routing this. 

 

Is it necessary? That depends on what you want to happen upon loss of lock. All registers are going to retain a static value should the clock stop due to loss of lock. Whether that's acceptable in your application is up to you. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
492 Views

I'm getting a similar error on a Cyclone V: 

 

Warning: RST port on the PLL is not properly connected on instance MAIN_PLL:MAIN_PLL1|MAIN_PLL_0002:main_pll_inst|altera_pll:altera_pll_i|general.gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock.  

 

I have the PLL set to "Auto Reset" to no avail. Tying the reset to the PLL locked inverted does not work. The PLL will just stay in reset forever. It worked in simulation, but not in the chip.  

 

I guess the only option is to tie reset to '0' and live with the hopefully erroneous warning.
Altera_Forum
Honored Contributor I
492 Views

You can't call it an 'erroneous warning' - it's perfectly valid and simply draws you're attention to the possible issue. If you have a glitch on your clock or PSU that causes the PLL to lose lock then it may not recover without a reset. 

 

If you have a mechanism whereby you can pulse the PLL reset in the event of the lock signal deactivating then you clearly should do so. If you don't then, as you say, you'll have to live with it. The question is how likely is the PLL to lose lock? Good question. However, if you have anything critical (in your mind) that can't cope with it losing lock then you need to design in a means of resetting it. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
492 Views

 

--- Quote Start ---  

You can't call it an 'erroneous warning' - it's perfectly valid and simply draws you're attention to the possible issue. If you have a glitch on your clock or PSU that causes the PLL to lose lock then it may not recover without a reset. 

--- Quote End ---  

 

 

Are you saying I can't rely on the "PLL Auto Reset" set to On in the Settings tab of the altera_pll wizard? I see in my poorly worded post I did not make it clear that it seemed to me the warning about needing a manual reset should go away.  

 

 

--- Quote Start ---  

If you have a mechanism whereby you can pulse the PLL reset in the event of the lock signal deactivating then you clearly should do so. If you don't then, as you say, you'll have to live with it. The question is how likely is the PLL to lose lock? Good question. However, if you have anything critical (in your mind) that can't cope with it losing lock then you need to design in a means of resetting it. 

--- Quote End ---  

 

 

I'm afraid I don't see any way of resetting it in our case. Hopefully, as long as the input clock is stable it won't lose lock but I'm a bit concerned about noise. About the best we could do is toggle power to the whole board if we lost communication with it.  

 

Thanks for the help.
Altera_Forum
Honored Contributor I
492 Views

No. I don't know that you can't rely on that setting - I'd have thought you can. Hence why you thought the warning isn't relevant - I see now. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
492 Views

There must be some official response from Intel about this somewhere. I can only imagine it's a very common question. Here are two solutions I have been using and found to work: 

 

- Connecting the reset port to an external pin tied to ground on the PCB 

- Using the PLL reference clock to generate a registered reset signal (e.g., using a counter or shift register) 

 

The second solution could be expanded to reassert reset when lock is lost, however I thought this was precisely what the auto-reset setting was for, and hence I see no reason why Quartus does not allow you to tie reset to zero internally as in older families.
PNaja
Beginner
492 Views

I also have the same issue when I upgraded from Quartus 17.1 to 18.01 and later on to 18.1.

  • The initial converted Arria 10 load compiled successfully
  • Then I changed NIOS clock from my device_clk (connected to external pin) to a clock bridge connected to 100 MHZ external clock trying to reduce the clock to the NIOS max clock rate of 50 Mhz. This change was done in the platform designer.
  • The RST_N error message is pointing to the two PLL's that were instantiated in the top level design and is not showing up in the platform designer.
  • The change had nothing to do with the PLL, Why are we getting compile error on the part of the design that was not changed.

 

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