We have a one design with following resource usage details.1. Stratx IV EP4SE820 : 29% of logic 2. Arria 10AX115 : 40% of logic Arria10 10AX115 is suppose to be the bigger in terms of gate count compared to stratix IV(EP4SE820 ), but the same design usage summary surprises me as ARRIA 10 usage is more compared to Stratix IV. Following are the after synthesis usage summary(synplify_premier) for two devices for the same design for your reference. Can you please provide us info on this? ##### start of area report# ####[
selecting part 10ax115n2f40i1sges
@n:fa174 : | the following device usage report estimates place and route data. please look at the place and route report for final resource usage. Total combinational functions 172148 of 427200 (40%) ALUT usage by number of inputs 7 input functions 0 6 input functions 43455 5 input functions 25761 4 input functions 16938 [=3 input functions 85994 ALUTs by mode normal mode 117556 extended LUT mode 0 arithmetic mode 44277 shared arithmetic mode 10315 Total registers 182343 of 854400 (21%) Total Estimated Packed ALMs 165849 of 213600 (77%) I/O pins 9604 of 650 (1478%), total I/O based on largest package of this part. Number of I/O registers Input DDRs :0 Output DDRs :0 DSP.M18X18_FULL: 382 DSP.M18X18_SUMOF2: 56 DSP.M27X27: 110 DSP.M18X18_PLUS36: 9 DSP Blocks: 557 ShiftTap: 0 (0 registers) Ena: 103452 Sload: 27196 Sclr: 14737 M20Ks: 74 (2% of 2713) Memory ALUTs: 528 (0% of 213600) Total ESB: 48123 bits # #### END OF AREA REPORT# ####] ##### start of area report# ####[ selecting part ep4se820f43c3 @N:FA174 : | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage. Total combinational functions 189852 of 650440 (29%) ALUT usage by number of inputs 7 input functions 3348 6 input functions 32577 5 input functions 29210 4 input functions 19875 [=3 input functions 104842 ALUTs by mode normal mode 126786 extended LUT mode 3348 arithmetic mode 47788 shared arithmetic mode 11930 Total registers 184820 of 650440 (28%) Total Estimated Packed ALMs 172059 of 325220 (52%) I/O pins 9604 of 1120 (858%), total I/O based on largest package of this part. Number of I/O registers Input DDRs :0 Output DDRs :0 DSP.Simple_Multipliers_9_bit: 6 DSP.Simple_Multipliers_18_bit: 335 DSP.Simple_Multipliers_36_bit: 35 DSP.Two_Multipliers_Adders_18_bit: 46 DSP.Four_Multipliers_Adders_18_bit: 10 DSP.Two_Multipliers_Adders_18_And_36_bit: 3 DSP Blocks: 120 (960 18-bit DSP elements). DSP Utilization: 100.00% of available 120 blocks (960 18-bit). ShiftTap: 0 (0 registers) Ena: 105847 Sload: 17898 Sclr: 11360 M144K: 0 (0% of 60) M9Ks: 32 (1% of 1610) Memory ALUTs: 350 (0% of 325220) Total ESB: 46570 bits # #### END OF AREA REPORT# ####] we have a design which is approx 9M gates(ASIC equivalent), can this fit in this single 10AX115 device? Thanks, Madhusudana
Without the design its very hard to comment. I do see that the S IV uses a lot less ram and manages to use a lot more if the ALM in 7 input mode.Have you tried compiling the design using the Quartus compiler? From talking to FAEs from Synopsys in the past, they admitted that Quartus was as good if not better than synplify.
The design file is encrypted and can not use altera tools directly for synthesis. I have done the mapping of the .vqm(vqm generated by synplify) using quartus, usage is 35%(came down by 5% compared to after synthesis usage).Please let me know if there is any directive to guide the tool to use ALM in 7 input mode?
Theres not really much you can do to guide the logic here in the mapping - it is what it is. There isnt much we can do to help.Altera may be able to help you more via mysupport.
I don't see any issue here. Your design in stratix uses 189852 of 650440 (29%)while in Arria it is 172148 of 427200 (40%) i.e. you are better off about 17k. Percentage figures are opposite because your Arria has less logic than startix