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Altera_Forum
Honored Contributor I
1,621 Views

Route HPS UART pins to FPGA pins DE0 nano SoC

Hi  

 

I am using a DE0 nano SoC and I need, for my VHDL design, the RX and TX signals from UART (I understand they are available just for de HPS Cortex A9), but in this case I need them to connect to FPGA. 

 

How can I get access to those 2 signals? 

 

Thanks.
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Altera_Forum
Honored Contributor I
372 Views

In the Qsys component for the HPS, go to Peripheral Pin tab and select FPGA from the drop down for UART. Refer to this if you need more help: 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an706.pdf
Altera_Forum
Honored Contributor I
372 Views

Thanks Sunchine, your reply has been very helpful. 

 

I have a new question about: In my case I don't need the HPS Cortex or its functions, I just need my FPGA design to communicate with Matlab by UART (using De0 nano SoC FTDI). When I get UART TX and RX pins by this way you recommend, do I need to make a C code program, address mapping o some steps to program the HPS too? 

 

I will appreciate your help, thanks.
Altera_Forum
Honored Contributor I
372 Views

Hi, you can actually use the UART IP in the FPGA if the HPS is not needed. Of course this means that you can't use the built in UART USB on DE0-Nano-SoC (since it is connected to the HPS UART). Search UART in the IP Catalog and you should see "Altera 16550 Compatible UART" and "UART (RS-232 Serial Port)" in the list. Note that I am using Quartus 16.0 

 

The user guide for these IPs are located here: 

https://www.altera.com/en_us/pdfs/literature/ug/ug_embedded_ip.pdf 

 

You will then need to connect the IP output to FPGA pins (for example, the DE0 Nano SoC has GPIO expansion header that you can use)
Altera_Forum
Honored Contributor I
372 Views

Thank you so much sunshine. 

 

Besides, my question is also if I need to make an address map of UART signals, a C program, or a boot image for SD card as well. Or simply, can I just use Qsys and my VHDL design for my problem?.
Altera_Forum
Honored Contributor I
372 Views

If I am not mistaken, the address map from Qsys will be placed inside .sopcinfo file, and you can use the "sopc-create-header-files" utility to create the C header files

Altera_Forum
Honored Contributor I
372 Views

Hello sunshine, 

 

I have done the similar process to enable UART1 using the FPGA option in Qsys. I want to access the UART1 using a Linux application running on the HPS. I have routed the Tx and Rx pins to GPIO_0 pins. Preloader and Device tree was generated and the SD card was updated.  

When I try to access the UART1 using 'open("/dev/ttyS1", O_RDWR | O_NOCTTY)' , I am able to get the file descriptor successfully. However any write to the UART1, does not produce any change in the GPIO pins. I have also verfied this by accessing directly the UART1 using 'echo 0xFF < /dev/ttyS1' . This produces no change in the pin voltage, verified using an oscilloscope. I am sure that the routing of GPIO pins is correct, since I have verified assigning '0' and '1' to other GPIO_0 pins and measured the voltages, which were correct.  

 

Do you have a hand on this? what could be the way to debug this further?
Altera_Forum
Honored Contributor I
372 Views

 

--- Quote Start ---  

Hello sunshine, 

 

I have done the similar process to enable UART1 using the FPGA option in Qsys. I want to access the UART1 using a Linux application running on the HPS. I have routed the Tx and Rx pins to GPIO_0 pins. Preloader and Device tree was generated and the SD card was updated.  

When I try to access the UART1 using 'open("/dev/ttyS1", O_RDWR | O_NOCTTY)' , I am able to get the file descriptor successfully. However any write to the UART1, does not produce any change in the GPIO pins. I have also verfied this by accessing directly the UART1 using 'echo 0xFF < /dev/ttyS1' . This produces no change in the pin voltage, verified using an oscilloscope. I am sure that the routing of GPIO pins is correct, since I have verified assigning '0' and '1' to other GPIO_0 pins and measured the voltages, which were correct.  

 

Do you have a hand on this? what could be the way to debug this further? 

--- Quote End ---  

 

 

Hello, 

 

Have you checked that he device tree in Linux has been updated to include the UART components?
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