Hello, I am trying to generate external UDP packets to send to my Arria V GX, and I need a port number to direct the packets towards. My FPGA is running the AN647 reference design from intel. How would I go about identifying the port number my FPGA is listening on?
I believe you are referring to software "source port" and "destination port" setting in UDP header frame.
You can refer to below wiki page to learn more about it.
and also TSE user guide (page 78, figure 40)
For Intel FPGA TSE IP, it only provide design solution until MAC layer. (as seen in AN647)
Any software stack design above the MAC layer is expected to be developed by user themself.
Thanks for your understanding here.
thank you for the response. Since the current implementation with the design reference only goes up to the MAC layer, is it still possible to communicate to a PC at that level, or is additional work to implement higher layers still necessary?
You will need to implement higher layer design if you plan to run Ethernet communication via PC in OS level like either Linux or Windows OS.