when I change board 25G clock to 322.26Mhz and Quartus set clock is 322.26Mhz, it can work fine. but when I change board 25G clock to 312.5 and Quartus set clock is 312.5, it is failed to cdr lock.
I did the following experiment, performed external loopback on the two 25G ports on the board, and found that CDR could not lock. it is locked on 322.26Mhz clock .
could give some advice for debug? Thanks a lot
As I understand it, you seems to observe some CDR lose lock issue in S10 devices. To ensure we are on the same page, just would like to check with you on the following:
1. What is the specific S10 device that you are using? ie L Tile, H Tile or E Tile?
2. What is the Quartus version used?
3. What is the specific IP that you are using ie Native PHY? Mind share with me the .ip file so that I could have a better understanding of the IP configuration. You may share a simple QAR with the .ip file as well.
4. Are you using any Intel devkit?
5. Just wonder if you are using duplex mode of the specific IP? If yes, would you mind to try enabling internal serial loopback to isolate signal integrity to see if the CDR can achieve lock.
6. Mind share with me how did you perform the board clock frequency change? Just wonder if you have had a chance to probe with oscilloscope to verify the frequency change.
Please let me know if there is any concern. Thank you.