Looks like your Stratix 10 design failed to go to User Mode. Are you using
Here's the things you can try:
Thanks for you apply.
I did some test like LED linking, and find it also failed with same error code .
by the way , the FPGA configuration clock source is external 125MHZ and generate 125Mhz to load image . is this should be check ?
Have you tried to reduce clock source to 50MHz? Is it you get the similar error?
Plus, when you program .jic file into Stratix 10, what is your TCK frequency used?
Can you kindly try to reduce your TCK frequency to 6 MHz ?
Below link is the command to change TCK frequency (on page 14= 2.8. Changing the TCK Frequency)
It has been a while since you have posted an update to this Forum thread. Do you have any update to me? Kindly get back to me if you still need my assistance.