S10 IO Pin Slew Rate

[BrixtonBan]

we are using a S10 FPGA on our design which one part of design emulates a SPI Slave device. When we run the design by connecting to another SPI Master, we are seeing failure on high frequency (50MHz clock), and from our debug we notice that the SPI Master/Host is driving the Clock and Data pin correctly, however the S10 IO was driving the Data pin at much worse slew rate (slower rising/falling rate), is there any configuration or constrain to improve the IO pin current strength or slew rate to improve the performance?

Diagram below is from oscilloscope capture on the 50MHz frequency. Top of the diagram, THC being our Master/Host that drive the signals, with much better slew rate, compared to the signal that is driven by the S10 FPGA on the lower part of the diagram.

[FvM]

Hi,
not much information given yet. IO-standard set for S10 data out (MISO) pin, connection length, load capacitance (PCB, cable, possibly additional intentional load capacitance), any series resistors or filters used,how is voltage probed?

MOSI and SCK don't look really good, by the way.

  

[Ash_R_Intel]

Hi,

Recommendations:

1) Check the IO standard that you are using.

2) Perform board level simulation to check the signal integrity of the board.

3) Adjust slew rate and drive strength of the pIn using Pin Planner: 2.2.2. Assigning Slew Rate and Drive Strength (intel.com)

Regards

[Ash_R_Intel]

Hi,

Hope my previous comment helped you to resolve your issue. As we did not receive any further comment, closing this case. However, it will still be open for the community users to comment on.

Regards