SDR SDRAM Controller MAX II

[MFric2]

Hey guys,

iam trying to Interface an SDR SDRAM from Micron with a MAX II CPLD.

Iam able to read between 10 - 400 Adresses but then i think because of timing issues the Read fails...

Because iam using an MAX II iam not able to get a PLL for the SDRAM Clock.... are there any reliable ways to Phase Shift the SDRAM Clock without a PLL ? Or does someone can give me tipps to constraint my Design with a Zero Phase shift ?

Currently iam driven the Controller and SDRAM with the same 100 Mhz clock from an external oscillator.

SDRAM : Micron MT48LC4M32B2B5-7 Max II : EPM1270

[NurAida_A_Intel]

Hi Sir,

You can try to constraint the output clock from the FPGA using generated clock constraint as explain in this link:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/timinganalyzer/clocking/tq-generate-clock.html

Hope this is helpful.

Thanks.

Regards,

NAli1

[a_x_h_75]

Are you issuing refresh cycles regularly enough? The fact you can successfully read something suggests to me it might not be a timing issue...

Cheers,

Alex

[MFric2]

Hey,

it has turned out that my sdram controller wont take care if there is a read request at the same time with an automatic auto refresh command so they overlap... which obviously fails