SDRAM Controller SDC Constraints

Altera_Forum · ‎02-09-2015

When using SDRAM Controller are SDC Constraints relative to SDRAM needed?

Thank you

Altera_Forum · ‎02-09-2015

Yeah, unfortunately the Altera SDRAM controller does not seem to create timing constraints like the DDR2/DDR3 IP core does.

I wrote some constraints for the DE0-nano SDRAM that are also valid for the SDRAM used on some of the other Terasic DE-series boards.

See the example design and SDC file posted in this thread;

Cheers,

Dave

Altera_Forum · ‎02-09-2015

Thank you very much for the example. Altera should document better their ip-core.