Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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SEU Detection Architecture

RHark
Novice
‎04-22-2019 05:19 PM
716 Views

Is the internal circuitry that performs the SEU detection fixed-in-place? As in, is it a hard-wired logic block that is only every used for the SEU IP, or is it implemented using logic cells that have other uses as well?

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JohnT_Intel
Employee
‎04-23-2019 05:52 AM
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HI, The EMR unloader is based on the Configuration block which is a hard block while the rest of the logic is built in FPGA core.
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