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Altera_Forum
Honored Contributor I
1,417 Views

SODIMM RAM interfacing with FPGA

Hi, I am working on High Performance Computing in low cost FPGA. So I have bought DE0-Nano (Cyclone 4) and I want to interface a SO-DIMM RAM with that Board. Physically it is possible I think, because in the Terasic, I have found a board "terasic tr5 fpga development kit (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=158&no=1001&partno=2)" which contains Stratix 5 GX (5SGXEA7N2F45C2N) FPGA and there is a socket of "DDR3 SO-DIMM" Memory, where u can plug upto 8GB of memory at a maximum speed of 933 MHz. If you seed the attached image, there you can see that DDR3 SO-DIMM memory sockets are connected with 64 pins of Stratix 5 GX FPGA though that Memory socket has 260 pins (https://en.wikipedia.org/wiki/so-dimm). So, I assume that we would require minimum 64 pins to connect a DDR3 SO-DIMM RAM to interface with FPGA. And in this context I can also say that DE0-Nano board has more than 80 GPIO Connections. So, It is physically possible to interface a DDR3 SO-DIMM RAM with DE0-Nano. 

 

So, have any one has done this kind of work then kindly help me out. Any help will be appreciated. 

 

Thanks In Advance.
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3 Replies
Altera_Forum
Honored Contributor I
200 Views

I dont know what is happening with the thread. So I am again posting it. 

 

Hi, I am working on High Performance Computing in low cost FPGA. So I have bought DE0-Nano (Cyclone 4) and I want to interface a SO-DIMM RAM with that Board. Physically it is possible I think, because in the Terasic, I have found a board "Terasic TR5 FPGA Development Kit" which contains Stratix 5 GX (5SGXEA7N2F45C2N) FPGA and there is a socket of "DDR3 SO-DIMM" Memory, where u can plug upto 8GB of memory at a maximum speed of 933 MHz. If you seed the attached image, there you can see that DDR3 SO-DIMM memory sockets are connected with 64 pins of Stratix 5 GX FPGA though that Memory socket has 260 pins. So, I assume that we would require minimum 64 pins to connect a DDR3 SO-DIMM RAM to interface with FPGA. And in this context I can also say that DE0-Nano board has more than 80 GPIO Connections. So, It is physically possible to interface a DDR3 SO-DIMM RAM with DE0-Nano. 

 

So, have any one has done this kind of work then kindly help me out. Any help will be appreciated. 

 

Thanks In Advance.
Altera_Forum
Honored Contributor I
200 Views

Hi, 

It is true that Stratix V support DDR3 DIMM. However, for Cyclone 4, it is not support any DDR3 protocol. 

you may refer to EMIf estimator for the EMIF support scheme in Cyclone 4. 

https://www.altera.com/products/intellectual-property/best-in-class-ip/external-memory/support-selec... 

 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
200 Views

It looks like the Cyclone IV and below series does not support DDR3 and later memory standards. The max support for Cyclone IV series is DDR2. If you want to use DDR3, you will need to go for Cyclone V, Stratix V, Arria 10 and higher devices.

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