SOPC/QSYS connect 32 bits avalon slave to a 8 bits SRAM

[Altera_Forum]

Hi everyone 

 my name is Alban, EE & embedded systems engineer, Strasbourg, France  I made and 512k x 8bits SRAM expansion for my Cyclone II EP2C8 dev board  i would like to make it accessible in the memory adress space of the NIOS  i made several attempts to make it work, but i'm still facing some problems  in SOPC i created a component with 8 bits readbyte/writebyte wide buses, and added some tristate logic into the VHDL file (i'm french i love VHDL ;)  the problem is that the duration of the read accesses is 4 times the duration of the write access. i think it occurs because of the 32 to 8 bit hidden adapter created by SOPC builder  i also tried to make a component 32 bits readbyte/writebyte wide buses, thus ignoring the 24 MSB and keeping only the 8 LSB, the duration of the read access is 1 as expected, but the read values are wrong  if i try to write 00 01 02 03 ..... 0E 0F in 16 successive byte adresses (module 16) i get this  0020FF40 : 03 00 00 00 07 00 00 00 0B 00 00 00 0F 00 00 00  0020FF50 : 03 00 00 00 07 00 00 00 0B 00 00 00 0F 00 00 00  0020FF60 : 03 00 00 00 07 00 00 00 0B 00 00 00 0F 00 00 00  0020FF70 : 03 00 00 00 07 00 00 00 0B 00 00 00 0F 00 00 00  0020FF80 : 03 00 00 00 07 00 00 00 0B 00 00 00 0F 00 00 00   the goal is to use the SRAM just as any external memory chip, with 8, 16 or 32 bits storage : one byte access for 8 bit storage, two bytes accesses for 16 bits, four bytes for 32 bits, and so on...  is someone kind enough to explain me what i must do ? i did not understand the avalon specifications  -> 8 bits or 32 bits avalon MM slave ? -> byteenables use or not ? -> how to configure properly the BSP ?  THANK YOU FOR HELPING Best regards Alban

[Altera_Forum]

hi it's me again 

 8 bits avalon MMslave seems to work, but not optimized for speed i verified all access types using my oscilloscope, trigged on the falling edge of the chip select signal  writes :  1> a char takes 1 write cycle.  2> a short int takes 2 write cycles. a short integer needs to be "2 bytes aligned" in memory 3> a int takes 4 write cycles. a short integer needs to be "4 bytes aligned" in memory  read : 1> a char takes 4 read cycle. the address bus spans all 4 bytes of a "4 bytes aligned" location in memory, and the NIOS selects the first, second third or fourth byte depending on the location of the byte that you need to read for 2> a short int takes 4 read cycle. same as above. the nios selects the first or the last two bytes. short int must be "2 byte aligned" 3> a int takes 4 read cycle. int must be "4 bytes aligned"  how do i create an avalon MM slave that allows reading times to be just as the same as the writing times ? do i need to use byte enables ?  THANK YOU FOR HELPING Best regards Alban

[Altera_Forum]

Unfortunately there is no fix for this, it is how the Avalon fabric translates a 32-bit read on a 8-bit slave. The only workaround I can think of is that you make your own 32-bit Avalon MM slave that will do the translation to 8 bit accesses itself, splitting one 32-bit request into 1,2 or 4 8-bit requests.

[Altera_Forum]

Unfortunately for you the Nios always asserts all 4 byte enables for reads. 

So there is nothing that external fabric can do to support byte reads from 8-bit memory.  I'm surprised about what you are seeing for writes. I though the bus width adapter always generated all four cycles, but generated some of them without the byte enable asserted.  Writes could, of course, be 'posted' and processed in the following clock cycles. That would help with some access patterns. It would help even more if the nios cpu itself had a build option to do posted writes. Posting writes and assserting the byte enables for Avalon reads should really be reasonably straight forward modifications.  I can think of a couple of ways of doing byte accesses - neither is very nice: 1) Map the memory so that high address lines force byte only accesses. 2) Access it through a clocked custom instruction rather than as an avalon slave.