SPI clock input and output pins on Intel FPGAs

[gyuunyuu]

Are there any special instructions that one must or should follow in pinout when there are SPI input and output clocks in the design? i.e are there specific pins that must be used for SPI SCLK input or output depending on the frequency of the SPI interface?

What I have found out so far which could be wrong is that if the SPI clock is going to be used to drive the clock signal of registers, then it must be input into an actual clock pin. However, if it shall not connect to register clock pin then we can use any general purpose I/O pin on the FPGA.

For clock outputs, I think it depends on whether the output clock comes from user logic or PLL.

I look forward to guidance from Intel AEs.

[gyuunyuu]

Any ideas?

[EngWei_O_Intel]

Hi

If you would like to use the clock in clock network, then you shall use clock pins.

Thanks.

Eng Wei

[gyuunyuu]

What problems should one expect if the clock pin is not used? Are those problems surmountable?

[EngWei_O_Intel]

Hi

If there is no timing issue, that should be fine. And only if the clock signal is not going to be ref clk for PLL usage.

Thanks.

Eng Wei