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The design works correctly in quartus prime (Lite edition 17.1) modelsim simulation, but when i program it onto an fpga, then it will not fucntional. I am using the Cyclone V 5CEBA7F31C8 FPGA. The main purpose is to generate a PWM signal using the SPWM technique. Moreover, it is extended for phase-shifted PWM
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Hi,
problem is that your sine ROM code isn't recognized by Quartus synthesis. A small modification based on Quartus ROM template makes it work.
Regards
Frank
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Since this is answered, do you have further question?
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As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions

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