SRIO clock via pll

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

SRIO clock via pll

1,123 Views

Hi,

I am connecting a TI DSP with my fpga cyclone IVGX (EP4CGX150CF23C7) using rapidIO interface (using rapidIO megacore function). I have a 250 MHz clock (that i feed to dedicated refclk pin). So I use this 250 MHz clock as an input to ALTPLL megacore function to get 125MHZ clock output that i feed to clock signal of rapid IO core via a CLKCTRL megacore function. When i compile, during fitter, i get following error:

Error (176350): Can't fit fan-out of node pll:PLL_block|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] into a single clock region

In some forums, it is being said that GPLL is being cascaded with MPLL in a wrong way.

But if i do the same procedure and replace rapidio block with PCIe hard IP block, the code compiles.

Any suggestion on how should I proceed?

thanks.

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.