SRIO clock via pll

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

SRIO clock via pll

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Hi,

I am connecting a TI DSP with my fpga cyclone IVGX (EP4CGX150CF23C7) using rapidIO interface (using rapidIO megacore function). I have a 250 MHz clock (that i feed to dedicated refclk pin). So I use this 250 MHz clock as an input to ALTPLL megacore function to get 125MHZ clock output that i feed to clock signal of rapid IO core via a CLKCTRL megacore function. When i compile, during fitter, i get following error:

Error (176350): Can't fit fan-out of node pll:PLL_block|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] into a single clock region

In some forums, it is being said that GPLL is being cascaded with MPLL in a wrong way.

But if i do the same procedure and replace rapidio block with PCIe hard IP block, the code compiles.

Any suggestion on how should I proceed?

thanks.

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