I have a STRATIX10 GX device :
1SG280HNF43 with JTAG ID CODE :
I have tried multiple clocks from the datasheet for this device but I'm unable to see any sample data. All I see are X's in the waveform.
Here are some of the clocks I have tried for this board:
Can you please help us figure out a CLK pin for this board that we can use as our PLL source.
May I know if your FPGA has entered user mode? Did you check if you have a clean source clock? Are you using signalTap and at which node you are seeing X's in the waveform? Do you have simulation run for your design? For clock connection, you can check on the pin functionality in pin connection guideline:
and also you can check on the pinout files here to match with the description in pin connection guideline:
Or you can also have a view and make assignment in pin planner.
Thank you for responding. We purchased the Stratix10 GX development kit and we were assuming the part number will be
Is this correct?
We are generating the waveform using Synopsys in house tools and don't see valid sample data. for the clocks mentioned above.
I am not the expert in JTAG Programming. I realize you have another thread discussing on it, perhaps you can continue to get the confirmation in the thread:
We need to make sure the FPGA is in user mode, before we looking for clock sample data. And also at which node you get the sample data?
How do I ensure the board is in user mode. Is there a switch I need to toggle physically on the board. I'm capturing sample using our in house synopsys tools. But the sample data on hw shows X's which I presume is because of the sampling clock not getting to the bus.
Sorry for late response due to my extended holidays. We can check the INIT_DONE signal to make sure the configuration is done and enter user mode.
We can refer to the flow is below doc:
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