STRATIX10 Maximum Pressure

[Benedict_Goh]

Hi, I would like to apply a Thermal Interface Material (TIM) to contact the STRATIX10 chip and a heatsink and I have a few questions: 

1. What is the maximum pressure that can be applied to the top side of the STRATIX10 chip without causing any damage or performance degradation? 

2. Is the maximum pressure the same for all variants of the STRATIX10 chip? 

Thank you! 

[Ash_R_Intel]

Hi,

Please check following webpage for general Thermal and Packaging documentation. Check AN659 (link available on webpage), for specific information.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/fpga-package-thermal.html

Regards

[Benedict_Goh]

Thanks for sharing the link. The variant that I am using is 1SM21CHU2F53 (package type is F2597) which has a lidded package. 

Do you have a reference for lidded packages? (Understand that AN659 is for unlidded packages) 

[Ash_R_Intel]

Hi,

I am checking with the internal team. Will get back to you as I hear from them.

Regards

[Ash_R_Intel]

Hi Benedict,

I got a chance to talk to the author of AN659 that I referenced earlier and enquired about the lidded package as well.

Turns out that the requirement remains the same for both lidded and lidless package.

You can also refer to following Knowledge article: https://www.intel.com/content/www/us/en/support/programmable/articles/000077198.html?wapkw=downward%20pressure

The information in the article is also present in AN659.

Regards