- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I want to use CPLD (10M16SAU324I7G) in my design with Intel Xeon D1746.
For that I need to have Allegro Cadence's schematic symbol & footprint of 10M16SAU324I7G.
You are requested to provide me the access for the same.
Also, I am referring doc "576513_Idaville_LCC_PDG_Rev2_2" for my custom board design. In this doc, the same CPLD is being used. I wanted to know whether you can provide me the driver or test/ bring-up codes (VHDL) of this Idaville board if possible.
Thank You
Raj Kumar
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello
Welcome to Intel forum. For Allegro Cadence's schematic symbol of 10M16SAU324I7G refer to link https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/fpga-schematic-symbols.html?elq_cid=4171900&erpm_id=2892549&q=10M16SA&s=Relevancy
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
We do not receive any response from you to the previous reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page