Hello all,I've been trying to build a very basic bit error rate tester (BERT) utilizing the Cyclone 5 starter kit (C5G), and was wondering if anyone could render some assistance. First, I'm incredibly new to FPGAs, VHDL, and related programming, so please be kind to any simple things I might be missing. What I'm trying to do is send out a 1 Gbps signal through the SFP-HSMC daughter card attached to my C5G, receive the signal, determine number of incorrect bits received (ie: BER), and display the BER utilizing the 4-character hex display on the starter kit. I've tried building the design from scratch to learn VHDL programming, and I've learned a fair bit about the programming; however, I've hit the point that I'm not sure if I'm transmitting/receiving the data correctly. At this point, I've ran into the following problems: 1. Am I transmitting my PRBS (which I've set and is not randomly generated right now as I'm unable to get the random number generator functions to work) correctly? 2. If I am, am I receiving it? I'm a bit confused on how I setup my VHDL code to transmit then listen for the received signal. I'm still getting used to the parallel processing nature and I'm not 100% sure how to read the RX pin from within a process after transmitting it using the TX pin. 3. Is there a simple way to read the BER? I had the thought of simply transmit pattern X, Read pattern X, compare received to transmitted using XOR, divide number of errors over transmitted bits, display BER on hex grid as "E-##" where# # is the number of zeroes before hitting my value (for instance 10^-9 be represented as "E-09". Basically, can the board handle real numbers such as 10^-9?) This part is relatively simple so I'm not worried about programming it, but is the chip capable of handling such numbers before I spend too much time trying to do so. Sorry for being long winded, but what I'm looking for can be boiled down to 2 things: Can anyone provide an example of a simple transmitter/receiver code for the C5G and is there a megafunction (similar to ALT4GXB ) for cyclone 5 chips? I'm looking for a quick solution sure, but I'd love to use this as a learning experience for VHDL just as much as getting the final product done. As such, example codes are more appreciated than simply debugging my code.
Hello again all,I'm still working on the design; however, while setting up the transmitter, I've run into a fitter error. Since I'm still technically working on the same project, I'll throw it in this thread. Error (14566): The Fitter cannot place 4 periphery component(s) due to conflicts with existing constraints (4 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. Error (175020): The Fitter cannot place logic pin in region (0, 23) to (0, 23), to which it is constrained, because there are no valid locations in the region for logic of this type. Info (14596): Information about the failing component(s): Info (175028): The pin name(s): HSMC_GXB_TX_p Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (184016): There were not enough differential output pin locations available (1 location affected) Info (175029): pin containing PIN_W4 Info (175015): The I/O pad HSMC_GXB_TX_p is constrained to the location PIN_W4 due to: User Location Constraints (PIN_W4) Info (14709): The constrained I/O pad is contained within this pin Does anyone know an exact solution? I've looked at the altera database for the error and it mentions that this is caused by my device having migration settings, but I'm not sure what that means or how to fix/disable it.