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Altera_Forum
Honored Contributor I
1,086 Views

Shared HPS pins pin planning on Arria 10

Hi to all  

 

I am working on HPS project in Arria 10 SX 320  

 

I have instantiated a SPI interface on shared pins and I would place pins with pin planner (the pins are dedicated to HPS and not shared to FPGA)  

 

On my qsf on brackets there is the name of hps pins  

 

 

set_location_assignment PIN_J18 -to spi_rhea_clk (SPI_M0_CLK) 

set_location_assignment PIN_H16 -to spi_rhea_cs (SPI_M0_SSN) 

set_location_assignment PIN_H17 -to spi_rhea_di (SPI_M0_MISO) 

set_location_assignment PIN_J19 -to spi_rhea_do (SPI_M0_MOSI)  

 

 

This location pinout are compliant to Arria 320 SX pinout but in the plan stage I've an error ,  

 

The error means that cannot place the pins on the pin location  

 

For example : 

 

Error(175020): The Fitter cannot place logic pin in region (84, 97) to (84, 98), to which it is constrained, because there are no valid locations in the region for logic of this type.  

Info(14596): Information about the failing component(s):  

Info(175028): The pin name(s): spi_rhea_di  

Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:  

Info(175015): The I/O pad spi_rhea_di is constrained to the location PIN_H17 due to: User Location Constraints (PIN_H17)  

Info(14709): The constrained I/O pad is contained within this pin  

Error(175005): Could not find a location with: IO_FUNCTION of HPS_IO (1 location affected)  

Info(175029): H17  

 

Error(175020): The Fitter cannot place logic pin in region (84, 95) to (84, 96), to which it is constrained, because there are no valid locations in the region for logic of this type.  

Info(14596): Information about the failing component(s):  

Info(175028): The pin name(s): spi_rhea_clk  

Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:  

Info(175015): The I/O pad spi_rhea_clk is constrained to the location PIN_J18 due to: User Location Constraints (PIN_J18)  

Info(14709): The constrained I/O pad is contained within this pin  

Error(175005): Could not find a location with: IO_FUNCTION of HPS_IO (1 location affected)  

Info(175029): J18  

 

 

How is solve this problem ? 

 

 

Best Regards
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1 Reply
Altera_Forum
Honored Contributor I
109 Views

Did you check if the correct package is selected in Quartus?

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