Signal Tap clock in trace window

[skyviper]

Can someone tell me how to add a reference clock to the trace window (data window)?

[FvM]

Hi,

not sure what you want to achieve.

Data is sampled with clock specified in signal configuration once per clock cycle, adding this clock to the trace window would just show a constant signal. It can be useful to show a lower frequency clock along with data, timing requirements may be violated if the clock isn't synchronous to acquisition clock. 

[ShengN_Intel]

Hi,

You can add the clock signal to the signal tap data window but you can't if the same clock signal had been used for Clock: in Signal Configuration.

[skyviper]

Why is that the case? You can't see the signals referenced to the clock to see if there is a timing issue. In step 5.3 of the Four Hour FPGA Lab it asks to answer the following questions. How can you answer these questions without the clock in the trace?

[ShengN_Intel]

Hi,

Yup, same clock signal can't be used in signal tap data window and Signal Configuration Clock: at the same time.

I think you can create another signal to get the clock signal then put that signal in data window for clock counting.

Thanks,

Regards,

Sheng

[sstrell]

There is no need to tap the sampling clock because each sample represents the rising edge of the sampling clock.  You can add cursors in the output waveform to count the number of samples between events, representing ticks of the sampling clock.

Signal Tap should not be used to solve timing issues because it only shows what's happening at the rising edge of that sampling clock.  The Timing Analyzer is for high speed timing analysis.

[ShengN_Intel]

Hi,

May I know do you have any further concern or update?

Thanks,

Regards,

Sheng

[skyviper]

Thanks. This answer makes not sense from a digital signal analysis perspective. I wish there was a forum to talk to a manager to plea my case as to why the reference clock should appear on the trace window.

[sstrell]

As I said, Signal Tap cannot be used to fix timing issues. It is for testing and debugging the digital functionality of a design only. If you really want to see a clock in the captured data, select a different signal as the sampling clock and add tap the clock you want to see. However, you’ll need to use an even faster clock as the sampling clock to get good resolution on the captured data for the clock you want to see.

[skyviper]

I do understand that. Its pretending to be a logic analyzer. Selecting a different signal defeats the purpose. Maybe there should be an appnote on what you're trying to tell me. Sure I can use a faster sampling clock but if that clock is in the wrong phase to the clock that I would be putting the trace window, I would be reading things in the wrong frame.

[sstrell]

Exactly. This is why you use the timing analyzer instead of Signal Tap to do this type of analysis.