Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Signal tap removal

Altera_Forum
Honored Contributor II
‎04-08-2011 05:23 PM
3,612 Views

Hi all 

I have an easy question. 

I compiled my design and then I appen signal tap analizer. It append to my design a new entity, "sld_signaltap:auto_signaltap_0". 

I run my design, made my analysis and now I would like to remove the entity.  

Well, I removet auto_signaltap_0.stp from my design, but the entity is still there.  

Any hint would be appreciated. 

Best regards 

 

Phate 

 

P.S. I use quartus2 10.1 web edition, so no incremental compilation or similar.
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Altera_Forum
Honored Contributor II
‎04-08-2011 07:49 PM
2,268 Views

Quartus includes instance information for signaltap in your QSF. The best way to remove this from your design and QSF is to: 

[1] remove the enable signaltap setting under the project settings 

[2] run analysis & elaboration
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Altera_Forum
Honored Contributor II
‎04-08-2011 08:22 PM
2,268 Views

And if that doesn't solve it, delete your /db and /incremental_db directories and try again.

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Altera_Forum
Honored Contributor II
‎04-09-2011 06:02 AM
2,268 Views

http://www.alteraforum.com/forum/attachment.php?attachmentid=3933&stc=1&d=1302328885

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