Signaltap fixes my problem??

[Altera_Forum]

I have a design (without signaltap) that shows a failure. Every attempt to connect signaltap to any signal (even 1 or 2 and the sampling clock) , the problem goes away.  

I have also seen where the problem goes away if I change something in the design that is not even related to the module that I suspect of having an issue. Recompiling the design with no changes always shows the failure.   Does anyone have any hints of can I do to try to capture the failure with signaltap?  So far I tried he following: Created a new clk from one of the PLL's to be used as the sampling clk for signaltap (to avoid affecting the clock domain of the suspected module) Minimize the number of signals to 2 or 3  Different hardware  I am using pre-synthesis signals   thank you

[Altera_Forum]

Sounds like you have some failing paths that then dont fail on recompile - have you got any ansync paths?

[Altera_Forum]

It's a different place-and-route that is fixing it, not SignalTap. You could run a bunch of seeds with SignalTap and hope it shows up again, but I wouldn't recommend it. Set the Top partition to Post-Fit(if you have any user created partitions, set them to post-fit too). This will lock everything down, including the failure. In SignalTap, you will only be able to tap post-fit nodes, and I would recommend just looking at registers as those are the most reliable, and you should be able to pin it down. 

Since you have fits that do work, you could also tap those same nodes and recompile everything, and if that image works, you can compare SignalTap between the working and non-working design.

[Altera_Forum]

Did you design pass Timing analysis? I think it is place-and-route too. But if you have constraint it and passed timing, with/without signaltap shouldnt affect, i think.