Simple Verilog Question--Impossible?

[Altera_Forum]

I have a verilog file Intensifier.v. In it is a module with the following port list: 

 module Intensifier (  clk,  _reset,  intensifierInput,  intensifierOutput  );  Now I have a top level file named Main.v. In it I want to instantiate an array of instances of Intensifier.  If I code: Intensifier [1023:0]intensifiers; I get the error: "Intensifier is not a type"  I am not surprised I get an error, as I have not instantiated Intensifier using a port list.  So, in Main.v I code: Intensifier intensifier(  .clk(clk),  ._reset(_reset),  .intensifierInput(mainTestIn),  .intensifierOutput(mainTestOut)  );  This does not give an error, but it is only a single instance of Intensifier, not an array of Intensifiers. Also, I have assigned mainTestIn and mainTestOut to intensifierInput and intensifierOutput, and if and when I can create an array of intensifiers, I will want each Intensifier in the array to have different inputs and outputs.  To be able to use different inputs and outputs, in Main.v I instantiate an instance of Intensifier using a port list but without assigning some inputs and outputs:  Intensifier intensifier(  .clk(clk),  ._reset(_reset),  .intensifierInput(),  .intensifierOutput()  );  This does compile without errors, but I'm not sure how I'll code .intensifierInput and .intensifierOutput later, and I still don't have an array of Intensifiers.  To get an array, if, in Main.v, I now try: intensifier [1023:0]arrayOfIntensifiers(  .clk(clk),  ._reset(_reset),  .intensifierInput(),  .intensifierOutput()  );  Or if now, in Main.v, I try: intensifier [1023:0]ArrayOfIntensifiers;  I get the same sorts of errors.  Is it possible to instantiate an array of Intensifiers in a similar manner as instantiating an array of reg:  reg [1023:0] myregs;

[Altera_Forum]

When I need to do this in VHDL, I use a for-generate statement. See if you can find the appropriate syntax for Verilog (or SystemVerilog). 

 Here's what it would look like in VHDL:   -- Some of these would probably be top-level ports ... signal _reset : std_logic; signal clk : std_logic; signal intensifierInput : std_logic_vector(1023 downto 0); signal intensifierOutput : std_logic_vector(1023 downto 0); ... g1: for i in 0 to 1023 generate u1: intensifier port map ( clk => clk, _reset => _reset, intensifierInput => intensifierInput(i), intensifierOutput => intensifierOutput(i) ); end generate; The syntax should be pretty similar. Do a search for generate in the Altera sopc_builder/ folder. I know I've seen examples in the Altera verilog code.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  wire [1023:0] mainTestIn; //wire or reg wire [1023:0] mainTestOut; //wire or reg  genvar i;  generate for ( i=0; i<1023; i=i+1 )  begin  Intensifier inst_i (   .clk ( clk ),  ._reset ( _reset ),  .intensifierInput ( mainTestIn ),  .intensifieroutput ( maintestout )  );  end endgenerate  --- Quote End ---    I think,you want like this.

[Altera_Forum]

Thank you Dave and Supal. You were both on the right track. Supal, your solution was almost perfect, but you forgot a block name. I added this in my final code, shown below, as "INSTANTIATE_INTENSIFIERS". 

 I really appreciate people helping each other out. So many folks seem to use the Internet for the purpose of putting others down.  Matthew  module Test1 (  //inputs  clk,  _reset,  testIn,    //outputs  testOut );   input clk;  input _reset;  input [1023:0]testIn;  output [1023:0]testOut;    wire [1023:0]testOutWire;  assign testOut = testOutWire;    genvar i;   generate  for ( i=0; i<1024; i=i+1 ) begin:INSTANTIATE_INTENSIFIERS  Intensifier intensifier (  .clk ( clk ),  ._reset ( _reset ),  .intensifierInput ( testIn ),  .intensifieroutput ( testoutwire )  );  end  endgenerate   endmodule

[Altera_Forum]

Hi Matthew, 

  --- Quote Start ---  Thank you Dave and Supal.   --- Quote End ---   You're welcome.    --- Quote Start ---   I really appreciate people helping each other out. So many folks seem to use the Internet for the purpose of putting others down.   --- Quote End ---   This forum has managed to stay quite civil :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I really appreciate people helping each other out. So many folks seem to use the Internet for the purpose of putting others down.  --- Quote End ---    Simple Concept : If we know something,we say otherwise we subscribe that thread. ;)  Pleased to help you.

[Altera_Forum]

How to implement this condition in verilog?? 

If input>500------> output= 500 If input<-500-----> output=-500 else --------------> output=input  This is my code for this: module check( clk,input,output);  input clk; input [15:0] input; output [15:0] output; reg [15:0] output;   always@(posedge clk) //negedge  if (input >= 16'h01f4)    output <= 16'h01f4;    else if (input <=16'hfe0c)    output <= 16'hfe0c;   else   output <= input;   endmodule  I don't known why i get wrong result!!! Need for helping!!

[Altera_Forum]

--- Quote Start ---  module check(clk,in,out);  input clk; input signed [15:0] in; output [15:0] out; reg signed [15:0] out;  always @ (posedge clk) //negedge   if (in >= 500)  out <= 500;    else if (in <= -500)  out <= -500;   else  out <= in;   endmodule  --- Quote End ---    Hopefully code will work now. ( too simple,isn't it? )  Problem :confused: : Operation was being performed as an unsigned one which is not your   requirement, it was performing 2's complement and then was   comparing. Solution :cool: : Declared signals as " signed" and make value as signed "500 or 16'sd500"   ( instead of 16'd500 ) right for comparison.  Note : Never give keyword name for declaring identifiers. :)

[Altera_Forum]

DEAR, 

Thanks man! I tried your code and it's ok.  But i don't know why when i didn't use "signed" to declare signals, it also is ok,however in >+500 and 0-500.  Anyway, thanks for your care! Best regards!