in several tutorials and examples the reset path is connected as in the picture.
However, it doesn't work for me. if I set the reset to "true" PLL simulation does not start. If I set the reset to "false", the PLL simulation starts, however the ADC simulation does not work.
The simulation works if I disconnect PLL Reset Signal from ADC Reset Signal (platform designer), And next I assign this signal in test-bench file (with negation)
My test-bench file looks like this:
initial begin reset_reset_n =1; assign modular_adc_0_reset_sink_reset_n=!reset_reset_n; clk_clk =0; #100000 modular_adc_0_command_valid =1; modular_adc_0_command_channel=0; reset_reset_n =0; end always #50000 clk_clk =!clk_clk; endmodule
the simulation works, but in the downloaded examples are different. Now I don't know what is correct ??
I found that the platform designer generates such code
adcSys_modular_adc_0 modular_adc_0 ( .clock_clk (clk_clk), // clock.clk .reset_sink_reset_n (~rst_controller_reset_out_reset), // this reset negation
Platform Designer generate code with reset negation in ADC instance. Is possible edit this??
When I manually remove "~" compiler generate error:
Error (10228): Verilog HDL error at adcsys.v(6): module "adcSys" cannot be declared more than once