Simulating F2H ACE-LITE interface on HPS.

[awaissman]

Hello,

I am finding that F2H ACE-lite interface in HPS IP have no implementation in simulation model.

All outputs on this interface not driven by HPS, and after tracing in to HPS i found that nothing connected.

Is HPS simulatin model support F2H interface?

Thanks,

[aikeu]

Hi awaissman,

I found this old design example as below as reference, hope it helps:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/exm-hps-axi-bfm.html

Thanks.

Regards,

Aik Eu

[awaissman]

Thanks for reference.

This design provide example for h2f AXI usage, I am looking for f2h direction that uses ACE AXI interface.

If you know where to find this example, please let me know.

Albert,

[aikeu]

Hi awaissman,

Sorry for the late reply.

For simulation there is this example for Agilex 5:

https://www.intel.com/content/www/us/en/docs/programmable/813752/24-1/fpga-to-hps-bridge-f2h.html

There is another example for datamover working with Nios and MSGDMA IP:

https://www.rocketboards.org/foswiki/Documentation/DatamoverDesignExample

Thanks.

Regards,

Aik Eu

[awaissman]

Hello,

Sorry for late replay.

We are using Agilex 7

I have tried to convert design but HPS conversion failed.

Do you have similar design for Agilex 7?

I will try run this design as is, need install support for Agilex 5 in to our Quartus.

Thanks,

[awaissman]

Hello,

We installed support for Agilex 5, and i tried simulate this design.

After opening Platform Designer and trying generate tb i am getting following errors:

Error: agilex5_hps_f2h_simulation_intel_agilex_5_soc_0.intel_agilex_5_soc_0: "MPU CCU Clock Divider" (MPU_clk_ccu_div) 1 is out of range: Div2
Error: agilex5_hps_f2h_simulation_intel_agilex_5_soc_0.intel_agilex_5_soc_0: "MPU Peripheral Clock Divider" (MPU_clk_periph_div) 1 is out of range: Div4
Error: Generation failed with exit code 3: 2 Errors, 3 Warnings

I will try fix them on my own, but hope you can help me with this.

Thanks,

[awaissman]

Hello,

I found provided directrory:

agilex5_hps_f2h_simulation_tb

When i tried compile tb in:

agilex5_hps_f2h_simulation_tb/sim/mentor

Getting following fatal error:

# --------- --------- --------- --------- --------- --------- ---------
# ** FATAL: Questa VIP version mismatch detected.
# ** There is a mismatch between the SystemVerilog (version = 20220701) and the BFM (version = 20240212).
# ** Please check your compilation and simulation commands to ensure a consistent QVIP version is in use.
# --------- --------- --------- --------- --------- --------- ---------

Not sure what wrong, first time I see SystemVerilog version problem.

Thanks,

[aikeu]

Hi awaissman,

Are you having the Quartus® Prime Pro Edition software version 23.4 or newer version in your setup?

Thanks.

Regards,

Aik Eu

[awaissman]

Hi Aik,

I have 24.2 quartus version.

Thanks,

[aikeu]

Hi awaissman,

Your version used is a Pro or Standard version?

Thanks.

Regards,

Aik Eu

[awaissman]

Hi Aik,

This is Pro Edition.

Thanks,

[aikeu]

Hi awaissman,

Sorry that I am not able to find the similar error which you have encountered.

At the moment there is limited support on the Simics simulation for Agilex 5 after the Agilex 5 hardware release. Thus unable to obtain much further information regarding the simulation error.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi awaissman,

I will close the thread if there is no further question.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi awaissman,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks.

Regards,

Aik Eu