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Valued Contributor III

Simulating Soft LVDS for Max 10

I'm working on an interface between an LTC 2264 ADC and a Max 10. The ADC has serial LVDS output, and I'm basically satisfied that I have a grasp on the use and configuration of the soft LVDS IP. I would like to simulate this design, using a testbench to inject simulated output from the ADC into my interface module. So, I wrote a simple Verilog testbench, with a clock block (i.e. always# 5 Clk = ~Clk) to simulate the output data clock, connected everything, and got an error in compilation: 


Error (15065): Clock input port inclk[0] of PLL "LTC2264:ADC|ADC_LVDS_Data:ADC_LVDS|ADC_LVDS_Data_0002:adc_lvds_data_inst|lvds_rx_pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block 

Info (15024): Input port INCLK[0] of node "LTC2264:ADC|ADC_LVDS_Data:ADC_LVDS|ADC_LVDS_Data_0002:adc_lvds_data_inst|lvds_rx_pll" is driven by _~1 which is COMBOUT output port of Combinational cell type node _~1 


What is the easiest way to generate a clock signal that will be acceptable for this IP?
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