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Valued Contributor III
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Simulation of timing analysis in ModelSim-Altera ??!!!

Hey guys , this is my first time to use the ModelSim-Altera analysis tool. I followed many tutorials and I know how to set the parameters of the TimeQuest and I get correct compilation of the TimeQuest with no unconstrained path nor negative slacks . The problem is that when I simulate the design using ModelSim (RTL Simulation) it works fine at any frequency as if its just functional simulation , so even when I work with clock much higher than maximum frequency it still works well. I want to know how to properly test the timing requirements of the design ??  

Thx in advance .
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Valued Contributor III
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It is likely without delay file so is functional, you can check delays directly on waveforms. Frankly I never used timing sim since functional + TQ analysis is adequate if you are experienced enough. timing sim is very slow and for big projects is unrealistically low that may take whole weekend to finish

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Valued Contributor III
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Thx Kaz , So u mean I do not need to check timing on waveforms if the TQ is giving correct results ? , I still need to see the exact timing simulation on waveforms ? so what would u suggest ?  

Another question is if I try design a fully combinational circuit , how do i get the timing analysis results (Max latency between Inputs and outputs) if i do not have any clocks ?
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Valued Contributor III
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Thx Kaz , So u mean I do not need to check timing on waveforms if the TQ is giving correct results ?  

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Provided your constraints are correct.  

 

 

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I still need to see the exact timing simulation on waveforms ? so what would u suggest ?  

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TQ takes care of delays and should be hidden from you unless you are having timing failures.  

For timing sim you add delay file to modelsim (called sdf if vhdl design) and when you open sim you add that file by clicking add. 

 

Alternatively old quartus sim had a handy timing simulator. 

 

 

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Another question is if I try design a fully combinational circuit , how do i get the timing analysis results (Max latency between Inputs and outputs) if i do not have any clocks ? 

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Can you explain that. All fpga designs are based on rtl. Unless you are doing some unusual cpld work. 

Delays may vary from build to build.
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Valued Contributor III
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Can you explain that. All fpga designs are based on rtl. Unless you are doing some unusual cpld work. 

Delays may vary from build to build. 

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Well , I mean for example if im designing an adder , thats fully combinational design which needs no clock , but to get appropriate timing analysis I have to make it work with clock like latch the operands into registers and latch the output . Im asking if there is some other way in which I can give up the clock and just get the latency between the inputs and output of the adder?
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Valued Contributor III
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Well , I mean for example if im designing an adder , thats fully combinational design which needs no clock , but to get appropriate timing analysis I have to make it work with clock like latch the operands into registers and latch the output . Im asking if there is some other way in which I can give up the clock and just get the latency between the inputs and output of the adder? 

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That is rtl we are talking about. combinatorial clouds sandwiched between registers. TQ takes care of delays as comb decisions are sampled at clock edge. if it passes timing you don't need to see delay values.
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Valued Contributor III
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That is rtl we are talking about. combinatorial clouds sandwiched between registers. TQ takes care of delays as comb decisions are sampled at clock edge. if it passes timing you don't need to see delay values. 

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I understand that concept , so eventually for circuits like adders , I would have to make it work through clocked registers to get the timing analysis ?
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Valued Contributor III
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--- Quote Start ---  

I understand that concept , so eventually for circuits like adders , I would have to make it work through clocked registers to get the timing analysis ? 

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You sandwich an adder between registers so that design works, not for sake of timing. Timing then has to pass. The idea is to sample data after say one clock then hand it to next stge. 

So one clock latency is inevitable but required. TQ checks that data I sampled on next clock edge and without violation of tSU/tH. 

The actual delay is then hidden from you
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Valued Contributor III
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--- Quote Start ---  

You sandwich an adder between registers so that design works, not for sake of timing. Timing then has to pass. The idea is to sample data after say one clock then hand it to next stge. 

So one clock latency is inevitable but required. TQ checks that data I sampled on next clock edge and without violation of tSU/tH. 

The actual delay is then hidden from you 

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Thx a lot Kaz :)
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