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SMS
Beginner
764 Views

Simulation script for project with multiple IPs

I am trying to simulate a project that has one instance of On-chip flash memory, multiple instances of Soft LVDS IP core and one instance of ALTPLL IP. When I try to simulate it gives this error:

"# ** Error: (vlog-7) Failed to open design unit file "C:/Users/Sarmad/Documents/Altera/TRR_Main_Digital_module_v1.1/LVDS_Channel_1_Tx.vo" in read mode.

# No such file or directory. (errno = ENOENT)"

It seems there is some issue with the simulation script. Is there a tutorial or guideline that details how to write or amend the simulation script in case of multiple IPs. Thanks

 

Regards

Sarmad

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12 Replies
AndyN
New Contributor I
362 Views

How did you generate your simulation script? Are you compiling each IP separately? The easiest answer is to go to Quartus Tools>Generate Simulator Setup Script for IP. This'll give you a single file to compile all of the IP in your project.

SMS
Beginner
362 Views

Simulation script for each IP core was generated automatically when the IPs were added to the project. And the whole project is compiled collectively. Actually the Quartus version that I am using (Quartus Prime 18.0 Lite Edition) does not have any such option in Tools menu. I tried to do the same from "Project > Upgrade IP Components > Generate Simulator Script for IP" but that button is not enabled (greyed out).

 

Moreover I have also tried adding a Nativelink setup simulation script (*.do) but that also doesn't make it work.

NBRUM
Beginner
362 Views

vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L work -voptargs="+acc" <module_to_simulate>

make sure that modelsim has those lib visible.

SMS
Beginner
362 Views

@NBRUM​ 

I tried this, though it didn't give that error but the IP cores does not generate any output. Instead they show white dotted line in the waveform. Any idea for this behavior?

SMS
Beginner
362 Views

I have also tried to setup simulation using command prompt (ip-setup-simulation) but it gives this error: "No spd files are included in quartus project", although .spd files for all the IP cores (except ALTPLL) are there in the project folder. Can anyone please suggest a solution or point me to a guide that one can follow in such a situation. Thanks

362 Views

May I know which device are you targeting? Found out that the ip-setup-simulation script was designed to work with family 10 devices and will not work properly with any other devices. As a workaround, you can use the ip-make-simscript that let you point directly to the spd files for each IP. You can find a brief description in Table 40 on the Intel® Quartus® Prime Standard Edition Handbook Volume 1 Design and Synthesis. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/archives/qts-qps-5v1...
SMS
Beginner
362 Views

I am using Max10 (to be exact 10M16SAE144I7G). I tried ip-make-simscript as well and it gave me the same error.

362 Views

Do you able to solve the issue? Do you need further help?

SMS
Beginner
362 Views

No, the issue remains unresolved. Yes definitely.

362 Views

Could you help to share your design? A simplified design that can duplicate the error is sufficient.

362 Views

1) You may have an invalid filename that you are trying to pass to vcom, eg., 

 

vcom c:/vhdl/my_vhdl_file.vhd 

 

would work, but 

 

vcom c:\vhdl\my_vhdl_file.vhd 

 

would not, since the backslash is a Tcl escape character, but

 

vcom {c:\vhdl\my_vhdl_file.vhd} 

 

will work, since it passes the path without interpreting the contents of {} 

 

2) You might also look for spaces in your paths. They can be used, but you have to use "" or {} to pass the path as a "single string".

tessellation
Beginner
338 Views

I had this or a similar problem trying to simulate IP cores with a Quartus Lite project in ModelSim. I am used to using Quartus Pro where you just generate a simulator setup script using that function under tools. However, that is not available with Quartus lite.

So there are base IP cores like counters, fifo and rom that don't create a .tcl file when they are generated. For these you just need to add a vcom for them in your .tcl or .do file.

For IP cores like fft and fir they do generate a .tcl file. Look in their simulation -> mentor folder and you will find it. Copy that .tcl and the whole simulator folder to you main project directory. With the .tcl in your main directory uncomment/fill in the appropriate lines, including vcom of the base IP cores.

Then you can just source <your tcl file>.tcl in model sim.

Hope this helps someone out there.

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