Thank you for your reply.
1: Still it is no clear to me - is the slow clock required for the soft LVDS to function properly or not? I could not find the slow clock also on the Technology Map Viewer. From the block diagram one would assume the serdes can be synchronized to slow clock, but as i understand it, this is not possible to acommplish. The proper synchronization can be achieved with bitslip function and test data only?
2. When you generate a Soft LVDS block you get some info:
Info: lvdstest: Using the external PLL mode requires that:
Info: lvdstest: (i) The fast clock (running at data rate /2) from the PLL feeds rx_inclock
Info: lvdstest: (ii) The outputs be registered in the logic fed by the receiver
Info: lvdstest: The receiver starts capturing the LVDS stream at the fast clock edge
3. I just tried a simple code and it seems it works just fine.
read_serdes_manual : process(clkfast_serdes)
begin
if rising_edge(clkfast_serdes) then
clkslow_serdes_last <= clkslow_serdes; -- edge detection
rx_dv <= '0'; -- default
rx_serdes_data <= rx_serdes_data(6 downto 0) & rx_serdes_i;
serdes_bit_cnt <= std_logic_vector(unsigned(serdes_bit_cnt) + 1);
if clkslow_serdes = '1' and clkslow_serdes_last = '0' then -- rising edge on slow clock
serdes_bit_cnt <= x"0";
end if;
if serdes_bit_cnt = x"1" then -- set fixed offset
rx_data <= rx_serdes_data;
rx_dv <= '1';
end if;
end if;
end process;
Regards
