Solution for a high-performance "translation" board

[Altera_Forum]

Hello, 

 I'm in the very initial stages of design of a card that should do the following:  * Receive data from 4-5 optical links. The data comes at ~200MBit/s per link - on a single data line, w/o a separate clock line (encoded in something similar, but not quite 8b/10b).  * Do some minimal processing and send the data to a gigabit ethernet link (most likely in raw UDP packets)  The total data throughput of the system is about 80 Mbyte / sec.  I want to implement this on a a single Altera FPGA. The throughput is too much for Nios II to handle, so I'm thinking about implementing it in VHDL. With the GbE MAC available as a core, I don't think it should be difficult.  A few questions: 

1. Which FPGA is most suitable for this task ? If possible I would like to do it without external CDR components. 
2. Are there any cores / components / techniques I should be aware of ? 
3. I want to find an evaluation board on which I'll be able to implement most of this application in the proof-of-concept stage. Any boards suitable ? I'm not sure about the availability of optical links, but at least receiving 4-5 inputs at 200MHz and a GbE output (RJ-45) will do. 

  Thanks in advance

[Altera_Forum]

Does anybody know if there are any parts out there that can still do CDR at 200 Mbps?  

 I believe Stratix II GX and Arria GX require at least 640 Mbps for CDR.  Stratix III offers a new "soft clock-data recovery" for the LVDS channels. You might be able to do that if you can interface with LVDS. I'm not sure what the restrictions are.  1 - At such slow speeds, you would normally oversample and extract the data. So you could bring the data into a Stratix II GX, Arria GX, or Stratix IV GX transceiver and sample at say 2Gbps.  2 - You've indicated you're using your own encoding so you're probably using your own protocol. The only IP I can think of that would be useful to you would be the GXB megacores and the Triple Speed Ethernet MAC. Your data throughput is high enough that you'll likely have to do all of the UDP/IP protocol in firmware.  Regarding oversampling. You have to write the code to due the data extraction and alignment. This isn't so bad. You basically look for bit transitions to determine the sampling midpoint. Then you pass the oversampled data to a phase alignment block which looks for a specific bit pattern and presents the over-sampled phase aligned data for processing.  3 - 200 Mbps (100MHz) is relatively slow so I don't think you'll have trouble having a board that can handle that. The only board I can think of off hand with any optical connectors is the Stratix II GX Audio / Video development kit and it certainly doesn't have 5 optical inputs. If you're going to use GX transceivers then you'll need a board that brings 5 of the transceiver inputs out to connectors.  I don't think there is a board that will exactly meet your needs but your best shots are probably: http://www.altera.com/products/devkits/altera/kit-dsp-professional.html and http://www.altera.com/products/devkits/altera/kit-signal_integrity_s2gx.html  Good luck,  Jake

[Altera_Forum]

Thanks for the detailed comment. 

 It surprises me that the built-in CDRs of Altera FPGAs can't handle this speed. I'm really reluctant implementing my own clock extraction in the FPGA since I have no experience with such things, but there are external CDR components that can handle such speeds and give me a clock + data, I think.

[Altera_Forum]

A viable and standard solution could be to use ASI protocol over optical interface, it supports up to 270Mbit/s per channel (it's a classical fibre channel application) and you can find ICs (Cypress, Gennum) and IPs (Altera has a complete ASI IP) for that job. In this way you won't have to design your own FW for clock and data recovery. 

But indeed you may try to design your own, it is a matter of enough oversampling ratio and some FIFO-aided technique of jitter reduction. It is a very interesting experience to design a CDR block.

[Altera_Forum]

--- Quote Start ---  A viable and standard solution could be to use ASI protocol over optical interface, it supports up to 270Mbit/s per channel (it's a classical fibre channel application) and you can find ICs (Cypress, Gennum) and IPs (Altera has a complete ASI IP) for that job. In this way you won't have to design your own FW for clock and data recovery. But indeed you may try to design your own, it is a matter of enough oversampling ratio and some FIFO-aided technique of jitter reduction. It is a very interesting experience to design a CDR block.  --- Quote End ---    Unfortunately I can not pick the protocol of incoming data - it is given as a requirement. So it seems I'll either have to implement the CDR in the FPGA or get a chip to do that.  There's an interesting AN from Xilinx on CDR implementation with 90 degree shifted PLL clocks:  http://www.xilinx.com/bvdocs/appnotes/xapp224.pdf

[Altera_Forum]

Hi eliben, of course you may try the HDL code that Xilinx suggests, I haven't checked about the complete portability to an Altera FPGA. Anyway it is not a hard concept, I think you may try to produce your own code. 

Anyway, have a look at: http://www.vitesse.com/products/product.php?number=vsc8228 it seems doing a good job for your application.  Cheers OD

[Altera_Forum]

If you can find an external IC that will do your CDR, that is actually the best way to go for your design. It will present you with your 100 or 200 MHz clock which you can drive into any FPGA. That way you wouldn't need a transceiver part and you can save some money. 

 Jake