Some trouble from using MaxplusII

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Some trouble from using MaxplusII

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Hi, all

Recently, i am engaging myself into CPLD developing. This is my first time to using Altera COLD. some trouble blocks me, need help from you.

How can i generate the .jed file for programming by MaxplusII project. I have get .pof, .jam, .jbc from my current project. Compiling tool is MaxplusII 10.2 Baseline.

If the .jed file is available, I program CPLD by MaxplusII programmer but it failed and show the message below:

"Error: "I/O error-corrupt '<path name><file name>.jed file"

what's wrong with it?

The third problem is how can i use the QuartusII programmer to load the jed file to CPLD?

Thanks a lot!]

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