Hi. I have the difficulty to understand the different of set_multicyle_path in system approach and skew approach(FPGA centric) in AN433 doc.
http://www.altera.com/literature/an/an433.pdf the constraint for system centric approach(pg14),
set_multicycle_path -setup -end 0 -rise_from [get_clocks
data_clock] -rise_to [get_clocks output_clock]
set_multicycle_path -setup -end 0 -fall_from [get_clocks
data_clock] -fall_to [get_clocks output_clock] the constraint for FPGA centric approach(pg26),
set_multicycle_path -setup -end 0 -rise_from [get_clocks
data_clock] -rise_to [get_clocks output_clock]
set_multicycle_path -setup -end 0 -fall_from [get_clocks
data_clock] -fall_to [get_clocks output_clock]
set_multicycle_path -hold -end -1 -rise_from [get_clocks
data_clock] -rise_to [get_clocks output_clock]
set_multicycle_path -hold -end -1 -fall_from [get_clocks
data_clock] -fall_to [get_clocks output_clock] Questions:
1. Why does the FPGA centric approach have extra 2 set_multicyle_path -hold compare to system approach?
2. What is the different between hold relationship with setup multicycle and hold relationship with hold multicycle (pg 26-figure36)?
thanks
