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Source Synchronous between 2 Altera FPGA

OrF
Employee
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Hi

I'm using the Methodology described at  " AN 433: Constraining and Analyzing
Source-Synchronous Interfaces
 " and in the web course "

https://learning.intel.com/developer/learn/course/168/play/1632:223/constraining-source-synchronous-interfaces

 

and I want to use (if possible ) the Setup and Hold output constraints . (Slide 31 in the course )  

or System-Centric constraint approach 

my system is 2 FPGA connected Stx10M - source-synchronous -SDR (15Mhz)  (via DIB bypass) or Via Cables - I don't think it matters in this case .

for the output delay

what I'm looking for  is the T-Setup and T-Hold of the "down-stream" FPGA ? where can I get the value ? 

is it the pure Tsu / Thold of the Input Resgister in the Down-Stream FPGA ? or I should retrieve it by any timing report ? 

 

a similar question goes to the Input Delay Values

where can I get the values Tco(Min/Max)  (Slide 15 - in the course)  of the External Device (which in my case is the again Stx10M) is it calculated value from timing report ? or is it simple the Tco of any Register in Stx10M 

Thanks

Or. 

 

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ShengN_Intel
Employee
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Hi.


1) Should be good enough for DIB interface. Probably needs to take the DIB Latency into consideration as well check this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html and this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html

2) Yes, Intel recommendation in "Source-Synchronous" methodology took into account the IO delay for the values of the T-hold / T-setup only for the register. External IO and Cable /PCB connection between the FPGA probably will need to take into account the extra latency.


Thanks,

Best Regards,

Sheng


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ShengN_Intel
Employee
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Hi,


Yes. Those are just simple Tsu, Thold, Tco for the register of external device. Probably can find those values from device datasheet.


Thanks,

Best Regards,

Sheng


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OrF
Employee
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Hi 

it seems it T-hold/T-setup are not simple to find the values - as far as I understand it is tightly coupled to the IO  supply / IO configuration 

therefore Intel provided the next process .

https://www.intel.com/content/www/us/en/docs/programmable/683103/21-3/generating-initial-i-o-timing-data-for-fpgas.html

I did the process , and I understand the Th / Tsetup values added IO to Register trace values / and impact by the IO supply/configuration   .

therefore I left with 2 gaps :

1) is it good enough for DIB interface (which does not have the IO. (connecting 2 dies of Stratix 10M)

  if not , from where can I get the real values ? 

2) in case I use External IO and Cable /PCB connection between the FPGA does Intel recommendation in "Source-Synchronous" methodology took into account the IO delay for the values of the T-hold / T-setup . or the values should be only for the register only ?

Or.  

 

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ShengN_Intel
Employee
397 Views

Hi.


1) Should be good enough for DIB interface. Probably needs to take the DIB Latency into consideration as well check this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html and this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html

2) Yes, Intel recommendation in "Source-Synchronous" methodology took into account the IO delay for the values of the T-hold / T-setup only for the register. External IO and Cable /PCB connection between the FPGA probably will need to take into account the extra latency.


Thanks,

Best Regards,

Sheng


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