Source synchronous constrains

[Lambert]

Hi all,

      Current source synchronous design, like lvds output,  if clk_o and data_o are output through lvds ip Core, and the phase  between load_clk & serial clock of clk_o and load_clk & serial_clk of data_o can be adjusted by the reconfigurable exteral Pll method,  is there necessary to do the source synchronous constrains for the io interface? I think it's not necessary and the result will be okay. If need, will the source synchronous constrains be related to the frequency of clk_o?

Best regards,

Lambert

[Kenny_Tan]

Yes, it is still needed. You may take a look at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf page 9.

Unless you want to make your signal asynchronous, otherwise the constrain of IO wrt to clk is needed.

[Kenny_Tan]

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[Lambert]

Hi KeenyT_Intel,

   The link you provided is one system synchronous part, I want to reserch source synchronous topic, and I don't fine one principle that can be used for source synchronous, if the output frequency can change freedomly.

B.R.

Lambert