Starting Process from another

[Altera_Forum]

Hi, 

 i got a design using two state machine. The first process is starting the second process and then it wait until its done. Both processes are clocked on the rising edge of the same clock.  The Code is like this:  PROCESS(clk, reset) BEGIN IF reset= ' 1' THEN  Start_S <= '0'; ELSIF rising_edge(clk) THEN  CASE state IS  WHEN start =>  Start_S <= '1';  state <= wait_on_ready;  WHEN wait_on_ready => Start_S <= '0'  IF Done_S = '1' THEN  state <= start;  ELSE  state <= wait_on_ready;  END IF;  END CASE; END IF; END PROCESS;  PROCESS(clk, reset) BEGIN IF reset= ' 1' THEN  done_S <= '0'; ELSIF rising_edge(clk) THEN  CASE state IS  WHEN wait_on_start => Done_S <= '0';  IF start_S = '1' THEN  state <= do_someting;  ELSE  state <= wait_on_start;  END IF;  WHEN do_someting =>  .....  state <= set_done;  WHEN set_done =>  done_S <= '1';  state <= wait_on_start;  END CASE; END IF; END PROCESS;  Now my question: Is it ok to turn on the Start_S (Done_S) Signals with the rising edge of the clock and turn them of with the next rising edge? Does the other process definitly get the signals high value when looking at them at the rising edge of clk or do i have to turn on the Signals for two clks? Or is it good practice to clock the second process with the negative edge?  Thanks in advance,  Patrick

[Altera_Forum]

You should only use the rising edge of the clock. As long as your design meets timing then you should have no problems with regards to clock edges.

[Altera_Forum]

Thanks for your fast response. 

 Could you please explain to me why this cant cause problems? I thought that if i set start_S with the rising edge and clear it with the next rising edge it is not sure that the signal is high when the clock edge arrives at the second process?!?

[Altera_Forum]

Because the signal will go low after the 2nd clock edge and the 2nd process will see the signal on the 2nd clock edge before it has been cleared by the first process.  

The timing analyser works all this stuff out for you so as long as you meet your set up and hold times then you don't need to worry about it.

[Altera_Forum]

Aha, ok i think now i understand it! 

 Many thanks,  Patrick

[Altera_Forum]

No problem

[Altera_Forum]

To explain fully: 

 Both processes will be running at exactly the same time becase they are sensitive to any event on the clock or reset. The first process will schedule "start_S" to change at the end of the current delta cycle, but it remain what is was for the this delta cycle, and as the other process is running at exactly the same time, it see start_S without change.  Now, if start_S was a variable or a shared variable, it really would be important when it was updated, and in the case of a shared variable, you'd have no idea whether it had changed or not by the time you were trying to read it. But you shouldnt worry about that because you shouldnt be using shared variables outside of testbenches anyway.