State Machine Controller for SOC FPGA/PLD

[BitBrain]

Long ago, I met an engineer that stated they had the license from Intel to modify the microcode.
Using this, would it be possible to use Intel microcode for a RISC processor, to run / control the design in the programmable devices or SOC's; thereby, eliminating the need for a processor and program memory? Hence, the controller state Machine would use modified microcode to run the programmed logic.

[_AK6DN_]

"Long ago, I met an engineer that stated they had the license from Intel to modify the microcode."

I met Santa Claus and the Easter Bunny long ago as well. They promised me lots of cool things.

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There is no "the microcode" from Intel. Microcode for which (I assume) processor? "Long ago" might mean 486 or pentium.

Anyway, doubtful any given engineer had an individual license for microcode source from Intel.

It would likely be a company, and in any event be under a very restrictive NDA.

Personally I doubt that "engineer" was being totally honest. Or you misunderstood what he had.

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"Using this, would it be possible to use Intel microcode for a RISC processor, to run / control the design in the programmable devices or SOC's; thereby, eliminating the need for a processor and program memory? Hence, the controller state Machine would use modified microcode to run the programmed logic. "

This makes no sense. RISC processors by design are not microcoded, thus they have no microcode.

Second, microcode is basically just a 'program' that takes the instruction set architecture (ie, like X86) and implements
it on the hardware resources of a given datapath/micro-engine. The input is still an X86 software program that implements
some functionality. So you still need program memory and a program as input.

So overall what you are asking does not make much sense. What is your real end goal?

[mabdrahi]

Hi BitBrain,

I will try to investigate about usage of Intel microcode for a RISC processor.

Thank you,

Aliff

[_AK6DN_]

You are wasting your time. BitBrain has no idea what they are asking about.

[BitBrain]

Aliff, Thanks for your support. In early 1980's, I worked with engineers who developed microcode for AMD bit-slice processors. The program was loaded into RAM for execution by the slice processors. The engineer I met claiming to use Intel microcode was from Mitre or MitreTek in Northern Virginia. That was in the 1990's. So, I'm thinking Intel microcode can be loaded into a RAM based state machine that controls FPGA's/PLD for various applications. Let's say the application is to make a very fast numerical engine or 1M point FFT that might have 1024 long data. Just a guess on something that's not need done. In the 1980's we did it for a speech processor and image processor using LPC microcode on AMD 2900.

[_AK6DN_]

"So, I'm thinking Intel microcode can be loaded into a RAM based state machine that controls FPGA's/PLD for various applications."

BitBrain, your misunderstanding is that there is a single thing that is "Intel microcode". There is not.

A microcode program is no different than any other software program. It is a sequence of instructions
that is implemented on some processor architecture that is designed to accomplish some task.

Running a microcode program from a writable control store on a custom bit slice processor implementation
is fundamentally no different than running an X86 instruction set program on your Windows PC. Or running an ARM
instruction set program on a new Apple Mx series computer.

Different program implementation languages and different processor architectures but not conceptually different.

So it appears back in the 90s some hardware engineer designed a custom AMD (probably AM2900 series) bit slice
processor datapath architecture and then a microcode engineer / programmer write some (micro)code to program
it and implement some functionality.

Conceptually you could do that now given a large enough FPGA. Implement AM2901 4b datapath slices in verilog.
Combine them together with other datapath entities (register files, etc) and a microsequencer. Add in some RAM
modules to provide a writable control store for your microcode program. And then write some microcode to do it.

[mabdrahi]

Hi Binoy,

After im consulting with other my team member, this case does not belong to our expertise.

We dont have much info about that. Apologizes for any inconvenience.

Thank you,

Aliff​

[mabdrahi]

Hi BitBrain,

Anymore question regarding this issue?, if I will close it soon

Thank you,

Aliff

[mabdrahi]

Hi Bitbrain,

Since we dont have any update from you, , I shall set this case to close pending. If you still need further assistance, you are welcome reopen this case within 20days or open a new case, someone will be right with you.

If you happened to close this case you will receive a survey. If you think you would rank your support experience less than 4 out of 5, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Thank you,

Aliff