Strange PLL Clock causing me failing paths in cyc V design

[Altera_Forum]

Dear all, 

 TimeQuest is warning me of a failing path in my Altera Cyclone V FPGA design.  It says failing path with:   Slack______From Node ____________________________________ ____to Node __________Launch Clock ____________________________________________________________________________Latch clock____Relationship __Clock Skew ___Data Delay -9.115 ____ io_control:io_control_inst1|data_out _______ dq _______ pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk ______ clk_100____ 10.000 ____ -10.144______2.901  I wonder what is the problem here and what clock divclk is? The entity io_control flops the data from inside the design and tristating it to dq. dq is an Input / Output Port at the top level design.  IO_control has clock input clk_100. clk_100 is routed globally through the design with an ALTCLKCTRL. The clk_100 is feed to external hardware via ALTDDIO which is consuming dq. Here is the code of IO_control:  flopping_data_out_proc : process(CLK, RESET)begin if (RESET = '0') then data_out <= (others => '0'); elsif (rising_edge(CLK)) then data_out <= Fin_DATA_ram; -- comes from inside FPGA Design end if; end process flopping_data_out_proc; mux_data_out_proc : process(slrd_en, data_out) begin if (slrd_en = '0') then DATA <= data_out; -- DATA is output of IO Control and wired to DQ else DATA <= (others => 'Z'); end if; end process;  Can somebody enlighten me if this is a critical issue? I set all needed timing constraints but wonder if I had to add a multicycle path or set false path between these clocks? It is noticeable that the fitter puts out a warning during fitting:  Warning (332049): Ignored create_clock at SDC1.sdc(2): Incorrect assignment for clock. Source node: CLOCK_50_B5B already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated. Info (332050): create_clock -name CLK1 -period 20.0   This is also the clock which feed the pll (clk_100) as reference clock. Can you help me clarifying this issue?    I added the archive file in the attachments. Thank you for any help.

[Altera_Forum]

You're using the same input port for 2 different clock domains. As the warning says, you should include -add to have both clocks input on the same port. Do you have something on your board that switches between generating 50 MHz and 100 MHz to this same port? 

 divclk looks like the output of your PLL.

[Altera_Forum]

--- Quote Start ---  You're using the same input port for 2 different clock domains. As the warning says, you should include -add to have both clocks input on the same port. Do you have something on your board that switches between generating 50 MHz and 100 MHz to this same port?  divclk looks like the output of your PLL.  --- Quote End ---    Hello, where do you see this? In the SDC file I have:  create_clock -name CLK1 -period 20.0 create_clock -name CLK2 -period 20.0 create_clock -period 10 -name clk_100   Clock_50_B5B is reference clock for the LPDDR2 Hardmemory Controller PLL (165.02 MHz + 330MHz). CLOCK_50_B6A is driving the 50 MHz instances on FPGA and is also the reference clock for the 100 MHz PLL.   Is this causing me the failing path warning in time quest? How do I have to interpret the failing path? Is not the above mentioned failing path telling me that I have a skew of 10 ns which is caused with the last flopping of output data in IO_Control?  There is no switching between 50 and 100 MHz.

[Altera_Forum]

Somewhere, you have another constraint targeting the port CLOCK_50_B5B based on the warning you got. Whatever that constraint is is part of what's messing things up. 

 The failing path report is indicating that clk_100, your virtual clock, is the latch clock for the failing path, implying that the failing path is an output path. Is this correct? Is clk_100 driving whatever device you are feeding? Check your set_input_delay and set_output_delay constraints. Make sure that the correct virtual clock is referenced in them (upstream device virtual clock for set_input_delay; downstream virtual device clock for set_output_delay).  Maybe just post your whole .sdc! That might make it easier to figure this out.

[Altera_Forum]

--- Quote Start ---  Somewhere, you have another constraint targeting the port CLOCK_50_B5B based on the warning you got. Whatever that constraint is is part of what's messing things up.  The failing path report is indicating that clk_100, your virtual clock, is the latch clock for the failing path, implying that the failing path is an output path. Is this correct? Is clk_100 driving whatever device you are feeding? Check your set_input_delay and set_output_delay constraints. Make sure that the correct virtual clock is referenced in them (upstream device virtual clock for set_input_delay; downstream virtual device clock for set_output_delay).  Maybe just post your whole .sdc! That might make it easier to figure this out.  --- Quote End ---    Thank you, sstrell. Yes, clk_100 (stems from an PLL and source ref clk is CLOCK_50_B6B) is driving also the external hardware, which is connected via hsmc adapter. clk_100 is outputed at ALTDDIO_OUT. And yes, the failing_path is an output path. I already set the constraints for the output path, but only the output delay. This is recommended from the manufacturer of the external hardware interface connected to my desgin. I also have a working example from the manufacturer where failing path are not occuring. :confused: What confuses me is the use of the word port and pin in vhdl language. I see that the create_clock command uses get_ports at the end, bu in my understandin CLOCK_50_B5B is an input pin and not a port?! I'm also using ALTCLKCTRL IP Cores to promote the outputs of the PLL through the device. Here is the whole SDC-File.   create_clock -name CLK1 -period 20.0 create_clock -name CLK2 -period 20.0 create_clock -period 10 -name clk_100 derive_pll_clocks derive_clock_uncertainty set_output_delay -add_delay -rise -max -clock 6.000 set_output_delay -add_delay -rise -max -clock 6.000 set_output_delay -add_delay -rise -max -clock 6.000 set_false_path -from -to set_false_path -from -to set_false_path -from -to set_false_path -from -to set_false_path -from -to set_false_path -from -to set_false_path -from -to set_false_path -from -to set_false_path -from -to set_false_path -from -to set_multicycle_path -from {ram_ip_control:ram_ip_control_inst1|avl_address*} -to {ram_ip_control:ram_ip_control_inst1|avl_writedata*} -setup -end 6 set_multicycle_path -from {ram_ip_control:ram_ip_control_inst1|cal_data*} -to {ram_ip_control:ram_ip_control_inst1|avl_writedata*} -setup -end 6 set_multicycle_path -from {ram_ip_control:ram_ip_control_inst1|avl_address*} -to {ram_ip_control:ram_ip_control_inst1|avl_writedata*} -hold -end 6 set_multicycle_path -from {ram_ip_control:ram_ip_control_inst1|cal_data*} -to {ram_ip_control:ram_ip_control_inst1|avl_writedata*} -hold -end 6   Again, CLOCK_50_B5B is only driving PLL of hardmemory controller. This has an additional sdc file (fpga_lpddr2_p0.sdc), which is auto generated. Perhaps herein lies the problem of double constraining the same clk? But then one may wonder how this could create a failing path at the output? CLOCK_50_B5B is not driving the clk_100.   Fitting the log says:  Info (332111): Found 27 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 33.333 altera_reserved_tck Info (332111): 20.000 CLK2 Info (332111): 10.000 clk_100 Info (332111): 20.000 CLOCK_50_B5B Info (332111): 3.030 DDR2LP_CK_n Info (332111): 3.030 DDR2LP_CK_p Info (332111): 3.030 DDR2LP_DQS_n_OUT Info (332111): 3.030 DDR2LP_DQS_n_OUT Info (332111): 3.030 DDR2LP_DQS_n_OUT Info (332111): 3.030 DDR2LP_DQS_n_OUT Info (332111): 3.030 DDR2LP_DQS_p_IN Info (332111): 3.030 DDR2LP_DQS_p_OUT Info (332111): 3.030 DDR2LP_DQS_p_IN Info (332111): 3.030 DDR2LP_DQS_p_OUT Info (332111): 3.030 DDR2LP_DQS_p_IN Info (332111): 3.030 DDR2LP_DQS_p_OUT Info (332111): 3.030 DDR2LP_DQS_p_IN Info (332111): 3.030 DDR2LP_DQS_p_OUT Info (332111): 3.333 pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph Info (332111): 10.000 pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk Info (332111): 3.030 ram_inst1|fpga_lpddr2_inst|fpga_lpddr2_p0_sampling_clock Info (332111): 3.030 ram_inst1|fpga_lpddr2_inst|pll0|pll_afi_clk Info (332111): 6.060 ram_inst1|fpga_lpddr2_inst|pll0|pll_afi_half_clk Info (332111): 15.151 ram_inst1|fpga_lpddr2_inst|pll0|pll_avl_clk Info (332111): 15.151 ram_inst1|fpga_lpddr2_inst|pll0|pll_avl_phy_clk Info (332111): 45.454 ram_inst1|fpga_lpddr2_inst|pll0|pll_config_clk Info (332111): 3.030 ram_inst1|fpga_lpddr2_inst|pll0|pll_dq_write_clk ...       EDIT:  Do I have to use create_generated_clock for clk_100 because clk_100 is not a clock which is coming into the fpga but is created via PLL from another clock? Could this be the problem and cause that timequest is reporting failing path?    Thank you.

[Altera_Forum]

You have clk_100 as a virtual clock. If it is actually an output clock, you need create_generated_clock at its output clock port (port is a top-level pin in SDC terminology; pin in the input or output of a cell) with the source as the output pin of the PLL and a false path to that output port as well so the path doesn't get analyzed as a data path. 

 You also need set_input_delay constraints and matching -min set_output_delay constraints.  As for the warning about dual clocks on one of the inputs, you'll have to look at/post the clocks report to see what's going on there.

[Altera_Forum]

--- Quote Start ---  You have clk_100 as a virtual clock. If it is actually an output clock, you need create_generated_clock at its output clock port (port is a top-level pin in SDC terminology; pin in the input or output of a cell) with the source as the output pin of the PLL and a false path to that output port as well so the path doesn't get analyzed as a data path.  You also need set_input_delay constraints and matching -min set_output_delay constraints.  As for the warning about dual clocks on one of the inputs, you'll have to look at/post the clocks report to see what's going on there.  --- Quote End ---    Ok, I tried to create generated clock, but have trouble matching the right ports:   create_clock -name CLK1 -period 20.0 create_clock -name CLK2 -period 20.0 create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk} -multiply_by 2 -duty_cycle 50.00 -name {clk100} # <---- Create generated clock command derive_pll_clocks derive_clock_uncertainty set_output_delay -clock -add_delay -rise -max 6.000 set_output_delay -clock -add_delay -rise -max 6.000 set_output_delay -clock -add_delay -rise -max 6.000   The log is telling me that  Warning (332174): Ignored filter at SDC1.sdc(5): pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk could not be matched with a port or pin or register or keeper or net or combinational node or node Warning (332049): Ignored create_generated_clock at SDC1.sdc(5): Argument -source is not an object ID  And fitter is then ignoring my set_output_delay commands.  I don't exactly know which output port of my pll I have to use for -source. I tried  - pll_inst_100|pll_100_inst|altera_pll_i|outclk - pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk - pll_100:pll_inst_100|outclk_0  but none is working. Always console say that it could not be matched with a port.  If I am properly informed I can choose my own name for the -name field? Do I have to set a target? When fitter ignores the create_generated_clock command because of wrong fields but then fitter is using derive_pll_clocks and creating the clock on its own:  Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|refclkin} -multiply_by 6 -duty_cycle 50.00 -name {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} Info (332110): create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|vco0ph} -divide_by 3 -duty_cycle 50.00 -name {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk}  When I then use pll_inst_100|pll_100_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk in my set_output_delay statements clock field fitter seems to set the output delays accordingly. At least he is not ignoring the delay output commands.  But then I will get in TimeQuest still failing paths: -3.890 io_control:io_control_inst1|data_out[14] dq[14] pll_inst_100|pll_100_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk pll_inst_100|pll_100_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 10.000 -4.949 2.861 4  Can I be sure that the output delay works and set_false_path for this? See attached picture and I have already attached the archive file.  Thank you so much so far.

[Altera_Forum]

--- Quote Start ---  You have clk_100 as a virtual clock. If it is actually an output clock, you need create_generated_clock at its output clock port (port is a top-level pin in SDC terminology; pin in the input or output of a cell) with the source as the output pin of the PLL and a false path to that output port as well so the path doesn't get analyzed as a data path.  You also need set_input_delay constraints and matching -min set_output_delay constraints.  As for the warning about dual clocks on one of the inputs, you'll have to look at/post the clocks report to see what's going on there.  --- Quote End ---    Ok, I tried to create generated clock, but have trouble matching the right ports:   create_clock -name CLK1 -period 20.0 create_clock -name CLK2 -period 20.0 create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk} -multiply_by 2 -duty_cycle 50.00 -name {clk100} # <---- Create generated clock command derive_pll_clocks derive_clock_uncertainty set_output_delay -clock -add_delay -rise -max 6.000 set_output_delay -clock -add_delay -rise -max 6.000 set_output_delay -clock -add_delay -rise -max 6.000   The log is telling me that  Warning (332174): Ignored filter at SDC1.sdc(5): pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk could not be matched with a port or pin or register or keeper or net or combinational node or node Warning (332049): Ignored create_generated_clock at SDC1.sdc(5): Argument -source is not an object ID  And fitter is then ignoring my set_output_delay commands.  I don't exactly know which output port of my pll I have to use for -source. I tried  - pll_inst_100|pll_100_inst|altera_pll_i|outclk - pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk - pll_100:pll_inst_100|outclk_0  but none is working. Always console say that it could not be matched with a port.  If I am properly informed I can choose my own name for the -name field? Do I have to set a target? When fitter ignores the create_generated_clock command because of wrong fields but then fitter is using derive_pll_clocks and creating the clock on its own:  Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|refclkin} -multiply_by 6 -duty_cycle 50.00 -name {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} Info (332110): create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|vco0ph} -divide_by 3 -duty_cycle 50.00 -name {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk}  When I then use pll_inst_100|pll_100_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk in my set_output_delay statements clock field fitter seems to set the output delays accordingly. At least he is not ignoring the delay output commands.  But still failing path with this message:  Slack______From Node ____________________________________ ____to Node __________Launch Clock ___________________________________________________________________________________________Latch clock____Relationship __Clock Skew ___Data Delay -3.890 io_control:io_control_inst1|data_out dq pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk 10.000 -4.949 2.861  Do I need to false path between this same used clock ?

[Altera_Forum]

--- Quote Start ---  You have clk_100 as a virtual clock. If it is actually an output clock, you need create_generated_clock at its output clock port (port is a top-level pin in SDC terminology; pin in the input or output of a cell) with the source as the output pin of the PLL and a false path to that output port as well so the path doesn't get analyzed as a data path.  You also need set_input_delay constraints and matching -min set_output_delay constraints.  As for the warning about dual clocks on one of the inputs, you'll have to look at/post the clocks report to see what's going on there.  --- Quote End ---    Ok, I tried to create generated clock, but have trouble matching the right ports:   create_clock -name CLK1 -period 20.0 create_clock -name CLK2 -period 20.0 create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk} -multiply_by 2 -duty_cycle 50.00 -name {clk100} # <---- Create generated clock command derive_pll_clocks derive_clock_uncertainty set_output_delay -clock -add_delay -rise -max 6.000 set_output_delay -clock -add_delay -rise -max 6.000 set_output_delay -clock -add_delay -rise -max 6.000   The log is telling me that  Warning (332174): Ignored filter at SDC1.sdc(5): pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk could not be matched with a port or pin or register or keeper or net or combinational node or node Warning (332049): Ignored create_generated_clock at SDC1.sdc(5): Argument -source is not an object ID  And fitter is then ignoring my set_output_delay commands.  I don't exactly know which output port of my pll I have to use for -source. I tried  - pll_inst_100|pll_100_inst|altera_pll_i|outclk - pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk - pll_100:pll_inst_100|outclk_0  but none is working. Always console say that it could not be matched with a port.  If I am properly informed I can choose my own name for the -name field? Do I have to set a target? When fitter ignores the create_generated_clock command because of wrong fields but then fitter is using derive_pll_clocks and creating the clock on its own:  Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|refclkin} -multiply_by 6 -duty_cycle 50.00 -name {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} Info (332110): create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|vco0ph} -divide_by 3 -duty_cycle 50.00 -name {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk}  When I then use pll_inst_100|pll_100_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk in my set_output_delay statements clock field fitter seems to set the output delays accordingly. At least he is not ignoring the delay output commands. But still failing paths. See attachement.  Thank you.

[Altera_Forum]

So you're essentially creating a source synchronous output. That generated clock should be after derive_pll_clocks in your file. Also, I don't see the output port name anywhere. Is it clk100? And you were missing get_pins for the -source argument. Here's what you should have: 

  create_clock -name CLK1 -period 20.0 create_clock -name CLK2 -period 20.0 derive_pll_clocks create_generated_clock -source {get_pins pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} -multiply_by 1 {get_ports <output port name>} -name clk100 derive_clock_uncertainty set_false_path -to {get_ports <output port name>} set_output_delay -clock -max 6.000 set_output_delay -clock -max 6.000 set_output_delay -clock -max 6.000 set_output_delay -clock -min <value> set_output_delay -clock -min <value> set_output_delay -clock -min <value   The extra generated clock is not creating the 100 MHz clock, so you can't have "-multiply_by 2 -duty_cycle 50.00" in that constraint. That's up to your PLL. Multiply by 1 is used because the clock at the output port of the device is the same as the clock output from the PLL. Timing analysis takes care of the delay between the PLL output and the output port.  See this online training for more details:  https://www.altera.com/support/training/course/ocss1000.html

[Altera_Forum]

--- Quote Start ---  So you're essentially creating a source synchronous output. That generated clock should be after derive_pll_clocks in your file. Also, I don't see the output port name anywhere. Is it clk100? And you were missing get_pins for the -source argument. Here's what you should have:   create_clock -name CLK1 -period 20.0 create_clock -name CLK2 -period 20.0 derive_pll_clocks create_generated_clock -source {get_pins pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} -multiply_by 1 {get_ports <output port name>} -name clk100 derive_clock_uncertainty set_false_path -to {get_ports <output port name>} set_output_delay -clock -max 6.000 set_output_delay -clock -max 6.000 set_output_delay -clock -max 6.000 set_output_delay -clock -min <value> set_output_delay -clock -min <value> set_output_delay -clock -min <value   The extra generated clock is not creating the 100 MHz clock, so you can't have "-multiply_by 2 -duty_cycle 50.00" in that constraint. That's up to your PLL. Multiply by 1 is used because the clock at the output port of the device is the same as the clock output from the PLL. Timing analysis takes care of the delay between the PLL output and the output port.  See this online training for more details:  https://www.altera.com/support/training/course/ocss1000.html  --- Quote End ---     sstrell, yes it should be a source synchronous output/input. I have an extern device with a 32 bit data word coming into fpga and fpga outputs data to it. The fpga acts essentially as FIFO.  I put generated clock now after derive_pll_clocks in my file. Also I added now the output port name which is pclk (see attached thumbnail view of RTL viewer)  https://alteraforum.com/forum/attachment.php?attachmentid=15539&stc=1  I also tired to implement the source clk in the create_generated_clock command:  create_generated_clock -source {get_pins pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} -multiply_by 1 {get_ports pclk} -name gclk100   However still no success and compiler left me with same warnings:  Warning: Ignored filter at SDC1.sdc(18): get_ports could not be matched with a port Warning: Ignored filter at SDC1.sdc(18): get_pins could not be matched with a port or pin   Sorry but at this point I'm at my wits end. I searched in RTL viewer and in Technology Map viewer (post fitting) for the pll divclk pin and it really is there. (see attached picture). But in RTL viewer divclk is not found. There it is just outclk of the pll. https://alteraforum.com/forum/attachment.php?attachmentid=15541&stc=1   https://alteraforum.com/forum/attachment.php?attachmentid=15540&stc=1 After the pll I connected the ALTDDIO. There is the net CLK_100 between them. And after ALTDDIO there is the output port of the top_level modul.

[Altera_Forum]

If you're getting name mismatch errors, use the Name Finder tool from the GUI dialog boxes you can access in the text editor to create SDC commands (Edit menu). The Name Finder lets you search the timing netlist directly, so the names are guaranteed to be correct. 

 Not sure why pclk port is not working for you since that should be coming directly from your HDL.

[Altera_Forum]

--- Quote Start ---  If you're getting name mismatch errors, use the Name Finder tool from the GUI dialog boxes you can access in the text editor to create SDC commands (Edit menu). The Name Finder lets you search the timing netlist directly, so the names are guaranteed to be correct.  Not sure why pclk port is not working for you since that should be coming directly from your HDL.  --- Quote End ---    Ok, with node finder in the TimeQuest gui (used the create_generate_clock button in the Constraints menu) I was finally able to create the correct constraint:  create_generated_clock -name {gclk100} -source .gpll~PLL_OUTPUT_COUNTER|divclk}] -master_clock {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk}   With this the generated clock was correctly created.   With  create_generated_clock -source {get_pins pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} -multiply_by 1 {get_ports pclk} -name gclk100  it is not. Seems to me quartus is rigorous how the constaints should be defined. Especially with the {} ...  One last question and then I will shut up: You mentioned in one of your last posts that I should false path to the output port with set_false_path -to {get_ports <output port name>} . What is the reason for this?  Thank you so much. Kind regards

[Altera_Forum]

The output clock path will still show up as an unconstrained output without the false path. The false path prevents any data path analysis since you're not using this as a data path.